SoC Synthesis & STA Engineer (f/m/div)
Are you passionate about innovation and creativity? Do you want to actively contribute to the development of next generation products? Then join a stimulating career opportunity for Connected Secure Systems in Bucharest, as SoC Synthesis and STA Engineer!
As a SoC Synthesis & STA Engineer you will:
- Take ownership of the timing closure throughout the entire RTL2GDS cycle (RTL synthesis, physical implementation and STA)
- Develop the block and full chip level timing constraints for different modes (incl. Interfaces (I2C, SPI, I3C)).
- Based on your UPF (Unified Power Format) knowledge implement low power designs and physical synthesis
- Develop/modify/run the flows for: RTL logic synthesis, logical equivalence checking, power intent verification and post synthesis timing validation.
- Collaborate with chip architecture, design verification, physical design, DFT, and analog teams to assure the tape out success.
- Drive the integration, timing, logical equivalence checking and analysis of various IPs into the SoC RTL
- Implement Timing ECOs to assure the full chip timing closure.
- Support the methodology and flows improvements related to timing constraint generation, analysis and timing closure.
- Work with your stakeholders to assure, that the RTL/Netlists are delivered on time and with the best quality, by developing checks for the QoDs at every stage of the design process.
You are best equipped for this task if you have:
- Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science
- 3+ years of experience working as a synthesis and/or front-end STA engineer
- Experience in ASIC multimode constraint generation and timing closure in different technology nodes.
- Experience with power intent and UPF at module and SoC level.
- Experience with logic equivalence checking and implementing functional ECOs
- Knowledge of technology timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA, crosstalk delay and noise analysis) and clock re-convergence pessimism removal
- Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime SI or equivalent)
- Experience with multiple clock domains, DFT/Scan and understanding of their impact on synthesis, physical design and timing closure
- Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
- Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
- Very good scripting skills (csh/bash, TCL, Makefile etc.)
- Self-driven with good technical leadership skills and ability to work in a dynamic environment