Staff Engineer

Infineon Technologies

Vadodara, Gujarat, India

Verilog System Verilog SystemVerilog ASIC RTL

Posted Feb. 6, 2024

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This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. Location: Gujarat
In your new role you will:

• This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.
• Architect and develop testbenches and environments.
• You will create, simulate, and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture, extract features, and define verification plans.
• You'll drive coverage analysis and closure, and collaborate with /support digital + mixed-signal co-simulations using System Verilog analog behavioral models.
• Working closely with Analog team and AMS simulation and verification.
• Define verification plan and verification architecture required for verifying required RTL
• Execute Defined test-plans to ensure bug free tapeout
• Develop required verification components.
• Test plan execution and debugging of RTL
• Meet verification targets (coverage closure, Regression clean-up)
• AMS verification will involve extensive testing of top level AMS simulation ( RTL + Spice)

• Bachelors/Master’s degree in Electronics /Electrical Engineering
• 3-10 years of Industry experience
• Digital DV
• Experience verifying complex IP with a track record of robust ASICs.
• Advanced knowledge of ASIC verification flows with SystemVerilog andUVM.
• Experience developing testbenches from scratch, bringing up design sin simulation.
• Skills with constrained random testing, coverage closure, and RTL /gate simulations.
• Proficient in a scripting language such as Python, Perl, Bash or similar.
• Exposure to AMS verification is a Plus and would be given preference
• Understanding of RTL + Spice simulation
• Willingness to learn basics of analog design
• Familiarity with VerilogA/SV-RNM and other modeling is an addedadvantage
• Basic Analog concepts like KCL, KVL etc.
• Exposure to AC2DC or DC2DC products is a great advantage
• Willingness to work with analog team for top level AMS verification.