Senior Engineer, Digital Design

InnoPhase, Inc.

Posted Oct. 28, 2023

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<div class="content-intro"><p><strong>About InnoPhase, Inc.</strong></p> <p><strong>INNOPHASE </strong>is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments.&nbsp; Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.&nbsp; To learn more about InnoPhase, visit <a href="" target="_blank"></a></p></div><p>In this job, you will be working with a team of digital design engineers to develop novel SoC products for connectivity and communications.</p> <p>The ideal candidate will be responsible for RTL coding, SoC specifications, and development, constraint file development, test plan development, functional verification, static timing analysis(STA), etc.</p> <p>This position is based in San Diego, Irvine, or San Jose.&nbsp;</p> <p><strong>Responsibilities</strong></p> <ul> <li>Develop specifications in communication and DSP areas to meet marketing and system requirements.</li> <li>Develop RTL (Verilog or VHDL), timing constraints, and detailed documentation.</li> <li>Perform CDC/Lint checks etc.</li> <li>Perform synthesis, STA, and logic equivalency checks. Implement ECOs.</li> <li>RTL &amp; gate level simulations.</li> <li>Create verification plans.</li> <li>Scripting with TCL, Perl, and Unix shell scripts.</li> <li>Develop DFT.</li> <li>Work with System, Software, RF, Analog, and Test teams and provide necessary support.</li> </ul> <p><strong>Qualifications</strong></p> <ul> <li>BS/MS EE/CS preferred</li> <li>5+ years of experience ASIC/RTL design, digital SoC development required</li> <li>Experience with wireless protocols, DSP and standard digital interfaces(such as AXI, AHB)</li> <li>Knowledge of VHDL, Verilog or SystemVerilog</li> <li>Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)</li> <li>Understanding of synthesis, static timing, DFT and digital SoC design flows</li> <li>Experience with ATPG, fault grading, scan, BIST, DFT a big plus</li> <li>Knowledge of SystemVerilog assertions, checkers, and constrained random verification techniques a Plus</li> <li>Knowledge of languages such as C/C++, Perl, Tcl or Python a plus</li> </ul>