Staff Engineer, Digital Design

InnoPhase, Inc.

Posted March 13, 2024

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<div class="content-intro"><p><strong>About InnoPhase, Inc.</strong></p> <p><strong>INNOPHASE </strong>is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments.&nbsp; Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.&nbsp; To learn more about InnoPhase, visit <a href="" target="_blank"></a></p></div><p>As a Staff Engineer, Digital Design, you will be working with a team of design engineers to develop novel 5G ORAN SoC products for connectivity and wireless communications. You will be contributing to micro-architecture and design of digital functional blocks based on product requirements. In addition to delivering high-quality digital solutions in the context of the product architecture, the team supports other disciplines with work products such as Verilog stimulus files, test benches for device bring-up/characterization, test vectors for product manufacturing, etc.</p> <p>This is a full-time position in San Jose, CA.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Design and integrate SERDES controller, PCS, PMA functional blocks</li> <li>Micro code development for network processor</li> <li>Network processor architecture, throughput analysis and optimization</li> <li>Front-to-back ASIC digital design and verification – RTL through physical implementation</li> <li>Define &amp; review synthesis constraints for functional blocks</li> <li>Functional issues debugging and timing closure issues debugging</li> <li>Work with System, Software, RF, Analog, and Test teams and provide the necessary support</li> </ul> <p><strong>Job Requirements</strong></p> <ul> <li>MS/Ph.D. EE/CS preferred</li> <li>10 or more years of experience in digital SoC development required</li> <li>Industrial design experiences PCIE/JESD/Ethernet controller &amp; PCS and respective SERDES PHY digital (PMA)</li> <li>Strong knowledge on CPU bus protocols and designs such as AXI/AHB/APB and DMA</li> <li>Solid design skill in Verilog / SystemVerilog RTL for complex SOC functional blocks in network products</li> <li>Solid experience in static timing analysis, defining timing constraints and exceptions</li> <li>Proficient in (Verilog/VHDL) and SystemVerilog RTL coding, LINT, CDC checking</li> <li>Experience in using Synopsys CoreConsultant IP generation tools is a plus</li> <li>Experience bringing highly integrated mixed-signal SoCs to commercial mass production</li> <li>Experience with embedded systems, wireless protocols, power management, signal processing, and standard digital interfaces</li> <li>Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques</li> <li>Knowledge of languages such as C/C++, Perl, Tcl, and Python</li> <li>Strong communication and presentation skills</li> <li>Team player with a strong sense of urgency to complete projects on time</li> </ul> <p><strong>Desirable Skills</strong></p> <ul> <li>Experience with Cadence F2B design tools</li> <li>Experience with formal verification tools</li> <li>Able to work effectively with incomplete or changing requirements</li> <li>Strong knowledge of mixed-signal concepts</li> </ul>