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Job Description
VLSI Concepts: Digital logic design fundamentals, Good RTL (VHDL or Verilog or System Verilog) writing skills, Scan and ATPG basics, Simulation knowledge
SKILLS REQUIRED :
Experience in RTL environments and Good RTL (VHDL or Verilog or System Verilog) writing skills.
Hands on experience with JTAG & IJTAG protocols, Scan and ATPG architectures and tools.
Scan and compression insertion
Scan and ATPG DRC analysis and fix in compression and bypass mode
Block Level and Top level ATPG pattern generation & coverage analysis.
Hands-on programming and scripting languages such as TCL/Perl/Python
Hands-on Simulation Debug and GLS (VCS, Verdi)
DFT: Hands-on design experience in DFT insertion and verification of Scan, ATPG, TAP and Jtag protocols using commercial test generation tools.
Tool set includes : Tessent Scan/ATPG, VCS, Fusion Compiler, Genus DFT, Spyglass, TetraMax, Primetime.
Enable the integration and validation of Test logic in all phases of the design and back-end implementation flows.
Programming : Hands-on expertise in Tcl, Perl, python, and Shell programming to write and understand scripting to automate and integrate the CAD flows for centralized deployment.
Problem Solving:
Strong experience in automation of methodologies/solution using TCL, Python, PERL and Tk.
Debugging experience to debug vendor tool problems and interacting with designers to help tackle their problems.
Possess excellent interpersonal and communication skills to collaborate and influence design development groups.
B.tech or M tech graduate with 2-4 yrs of experience
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Other Locations
IN, Hyderabad
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
