DFX Design Engineer
CEG HIP MYS organization is holding the charter to develop end-to-end DDR IP and software development as a path to enable new markets and organizational capabilities leveraging world class IPs and highly talented end-to-end firmware and silicon testing capabilities. CEG HIP MYS will collaborate closely with SOC and customer organizations to develop the platforms.
With this opportunity, you will have opportunity to expand your exposure in industry SoC development, IP leadership PHYs, industry soft IPs, SoC and IP subsystems implementation and testing.
Key Responsibility include :
Develops and implement design for test (DFT) structures for complex IP.
Determines design for test approaches and develops DFT architecture for IP and SOC.
Designs and verifies DFT structures for JTAG network, Bscan, Scan, memories (MBIST), digital and analog circuitry.
Performs scan synthesis.
Creates, simulates and verifies automatic generated test patterns (ATPG).
Creates functional tests and corresponding test patterns.
Test Mode timing constraints development and DFT mode timing closure.
Knows about failure mechanisms in silicon production and creates test algorithms.
Supports silicon bring up of test patterns.
Performs diagnosis of test patterns on silicon and optimizes test time.
Enable Pre-si validation on IP and support SOC level
Bachelor's degree in engineering, Electrical Engineering, Computer Science or related field.
Candidate will have 2-5 years of hands-on experience with mixture of Logic Design and or PreSilicon Verification or DFX design.
Candidate must possess strong fundamentals on the following area.
Good understanding in SV, OVM, UVM and verification methodologies
Experience in using verification tools such as VCS DVE Verdi etc.
Extensive coding experience that includes logic, behavioral modelling, SV coding
Strong fundamental knowledge of HW description language Verilog and assertion coding and logic simulation
Strong in problem solving debugging various simulation failures and formal verification
Strong written and oral communication skill able to communicate well with counterparts and key stakeholders including cross site partners.
Knowledge in advance DFT methodology including ATPG, MBIST, JTAG, Bscan [ IEEE 1149.x ] as a plus.
Experience in IP/SOC integration is an added advantage.
Good understanding in High-Speed IO Design and Mixed signal design Possess as added advantage.
Experience with post silicon debug is an added advantage.