Emulation/Post-Si Validation Engineer
- Bachelor Degree in Electrical & Electronics Engineering or Master Degree in Electrical and Electronics Engineering or Computer Engineering
- Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si.
- Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PCIE/DMI/DDR/Mem et.al.
- Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware.
- Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation.
- Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis.
- Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers.
- Knowledge in RTL design, VHDL/Verilog is a plus.
- Strong analytical ability, problem solving and communication skills
- Ability to work independently and at various levels of abstraction
Technical Individual Contributor, hands on technical expert
8 – 12 years of experience
Bachelor Degree in Electrical & Electronics Engineering or Master Degree in Electrical and Electronics Engineering or Computer Engineering
Excellent programming skills (C, C++, Perl, Python, Tcl, etc.) with understanding of firmware-hardware codesign and development
Proven experience in implementing Low level Driver/Firmware, SW/FW interface design and deep insight into the hardware internal architecture and flows.
Ability to understand the firmware requirements and design testbench, testplans for validating firmware in an fpga emulation.
Proficiency in various hardware Debugging Tools, methodologies using Pre-Silicon Emulator and Post Silicon Boards for issues in the hardware-software boundaries.
Good understanding of Networking protocols and Signal processing algorithms/flows in hardware.
Experience in ARM, DSP, Micro-controller low level embedded software programming including HW configuration, state machine design with timing constraints.