Formal Verification Engineer
- Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs (Graphics, Server IPs, processors and SOCs) .
- Using the hardware architecture design and RTL implementation details, define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design, Carve out the right boundaries for the design, create comprehensive Formal Verification test plans, track, verify, apply abstraction techniques and converge on complex designs to deliver a high quality design on schedule and articulate the ROI.
- Analyses new methodologies, evaluates new tools and corroborate results.
- May work with vendors on resolving hard design and tool problems.
- Bachelors Degree in Engineer (Electrical Engineering, Computer Science or a related field with 3-5 years of experience or (Master's Degree with 1 year of experience in related field
- As a Datapath Formal Verification Engineer, you will be responsible for ensuring the correctness and reliability of complex digital circuits within the datapath of integrated circuits (ICs).
- You will utilize formal verification techniques to mathematically prove that the datapath design meets its specified functionality, without relying solely on simulation-based testing.
- Strong understanding of digital design principles, datapath architecture, and arithmetic units.
- Proficiency in formal verification methodologies and tools.
- Experience with hardware description languages (Verilog, VHDL) and formal verification languages (SystemVerilog Assertions, PSL).
- Familiarity with industry-standard formal verification tools.
- Excellent problem-solving and debugging skills.
- Effective communication and teamwork abilities.
- Must have understanding of digital design principles and good to have Verilog/c++ language