IP Verification Engineer
- Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement:- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 7-10 years of industry work experience, or- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-9 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications:- 5+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience.- 5+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools.- 5+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE.- 5+ years of experience in OVM/UVM for developing verification test benches and constrained random verification.
Experience with Ethernet, Network packet processing needed
1-2 yrs of experience with Formal verification using JasperGold or similar tool is preferred
Experience with PCIE is nice to have