Logic Design Engineer
This position is within the Design Enablement (DE) organization of Intel Technology Development group. We are looking for a talented individual to join ASIC Testchip team to work on IP-SoC frontend logic and validation.
In this role, responsibilities include although not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrate and validate IPs at the SoC level.
Performs functional verification of IP logic to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the pre-silicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Bachelor Degree (Master Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or other related field of study
5+ years of relevant experience in VLSI design and Verification/validation tests.
Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.
System simulation models, and debugging RTL/tests.
Analytical with good interpersonal skills
Excellent team player
Strong analytical ability, problem solving and communication skills
Willingness to work independently and at various levels of abstraction.