Logic / Validation Engineer
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Follows secure development practices to address the security threat model and security objects within the design.
Works with IP providers to integrate and validate IPs at the SoC level.
Drives quality assurance compliance for smooth IPSoC handoff.
The ideal candidate will have the desire and ability to learn logic and validation skills
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor´s degree in Electrical Engineering, Computer Engineering, Computer Science or related degree and 1+ years in RTL design or logic design or verification or validation
Intern experience in semiconductor industry
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.