Physical design Engineer (Synthesis, Automatic Placement and Route)


Posted Feb. 12, 2024

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Job Description

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.


Candidate must have 3+ years of relevant experience with Master's degree (M.Tech / MS) in Microelectronics/ Electronics Engineering or equivalent qualification from reputed institute.

Candidate should have worked on block closure using industry standard tool for SAPR ( Synthesis , Automatic Placement and Route) flow. Candidate should have good knowledge of Floor planning, Power planning, Placement, Clock Tree Synthesis and Routing. Candidate should be well versed with multiple optimization options for design closure and expected to sign off design, with complex implementation issues, using industry standard tools.

Candidate should have good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure. Candidate should have worked on Timing and Layout closure for the blocks, ensuring DRC, LVS, density and Antenna requirements are met as per specification. Candidate should have good knowledge of top-level Integration issues to ensure block level deliverables meet project level requirements for timing and layout closures. Experience in closing design in 10nm and lower technology with frequency target of 2 GHz and higher will be preferable.

Candidate should have good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design. Knowledge and exposure to Synthesizable Verilog / System Verilog, RTL coding for ASIC designs and Simulation tools will be plus.

Any scripting language experience, like Perl, TCL, python would be added advantage.

Candidate should have good analytical, problem-solving skill for debugging issues faced at work. Candidate should have proactive and transparent communication. Candidate should be having mindset to work in diverse and collaborative environment with teams in adjacent functional domains and different Geos.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.