Physical Design Engineer ( Synthesis , Placement and Routing )


Posted Feb. 12, 2024

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Job Description

Design Enablement team at India, is part of Technology Development group, having charter to develop methodology for advance process nodes, providing opportunity, to be among the first one to work on latest technology. This role, in Design Enablement, is for experienced Individual contributor for Physical design, using Synthesis -Automatic Placement and Route flow, from RTL to GDS , including sign off for Timing, Reliability and Layout verification, using Industry standard tools for APR partitions with high frequency targets. Candidate is expected to work on Synthesis, Floor planning, Placement, Clock Tree Synthesis, Routing, Timing convergence, Scan, Hard Macro integration, and Physical convergence. Candidate will be collaborating for, constraint development, flow optimization to meet design requirements, by working with RTL developers, CAD team and EDA vendors. Candidates should possess expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. They should optimize design to improve productlevel parameters such as power, frequency, and area. This role also requires understanding of analysis and sign off flow for project, and candidate should be able to resolve issue in implementation, by working with CAD team and EDA vendors. Candidates should participate in the development and improvement of physical design methodologies and flow automation. This role requires transparent and clear communication and mindset to excel at work in collaborative environment with teams in adjacent functional domains and different Geographic locations


Candidate must have 3+ years of relevant experience with Master's degree (M.Tech / MS) in Microelectronics/ Electronics Engineering or equivalent qualification from reputed institute. Candidate should have worked on block closure using industry standard tool for SAPR ( Synthesis , Automatic Placement and Route) flow. Candidate should have good knowledge of Floor planning, Power planning, Placement, Clock Tree Synthesis and Routing. Candidate should be well versed with multiple optimization options for design closure and expected to sign off design, with complex implementation issues, using industry standard tools. Candidate should have good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure. Candidate should have worked on Timing and Layout closure for the blocks, ensuring DRC, LVS, density and Antenna requirements are met as per specification. Candidate should have good knowledge of top-level Integration issues to ensure block level deliverables meet project level requirements for timing and layout closures. Experience in closing design in 10nm and lower technology with frequency target of 2 GHz and higher will be preferable. Candidate should have good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design. Knowledge and exposure to Synthesizable Verilog / System Verilog, RTL coding for ASIC designs and Simulation tools will be plus. Any scripting language experience, like Perl, TCL, python would be added advantage. Candidate should have good analytical, problem-solving skill for debugging issues faced at work. Candidate should have proactive and transparent communication. Candidate should be having mindset to work in diverse and collaborative environment with teams in adjacent functional domains and different Geos

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.