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Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.
You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with preferably up to 6 years of relevant experience in the industry. (Number of years of experience is not a deterrent for this position and we are more looking for right skillset and attitude.) Additional qualifications/skills include: 1. Experience in developing high quality validation plans, collecting and analyzing the test results and being able to debug the failures to RTL/gate/schematic level 2. Strong problem-solving and teamwork skills, and strong verbal and written communication skills 3. Ability to produce results in a challenging, fast-paced, multi-site, multi-group environment 4. Good working knowledge of HDLs and HVLs like VHDL, Verilog HDL, SystemVerilog is a must. 5. Good working knowledge of either one or more of reuse methodologies like VMM/OVM/eRM/AVM/RVM, preferably UVM. 6. Good understanding of IO design and validation methodologies, and electrical and system validation issues related to analog, digital, and mixed-signal circuits/IPs would be a big plus. 7. Understanding of design-for-testability and design-for-reliability methodologies would be a big plus. 8. Work experience with at least one other verification aspects like Performance modeling, Formal verification, Gate Level verification, Emulation, etc. would be an added advantage. 9. Proficiency in scripting languages and utilities including Make, Perl, Python, etc. will be a bonus. 10. Experience in mixed signal IP design verification is a plus with protocols such as PCI-Express, USB, Display Port, Ethernet, DDR etc. and AMBA, JTAG, PIPE, etc. is desired 11. Should be able to contribute as Individual Contributor or technically leading a group of team members as per requirements
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.