Pre Silicon Verification
Job DescriptionPerforms functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Candidate must have a B.Sc. or MSc in Computer Science / Electrical Engineering.
- At least 5 years of hands-on experience in chip verification from block-level to full-chip.
- Creating and optimizing the complex validation environment and generating focused and random test cases, analysing coverage and debugging failure cases
- Expertise in vertical and horizontal reuse of verification components
- Proficiency in SystemVerilog UVM
- Strong problem solving and debugging skills
In addition to the qualifications below, the ideal candidate will also demonstrate:
- Great interpersonal skills, and ability to inclusively collaborate with others in group and outside the group
- Willingness to work closely with various chip design disciplines and cross site teams
- Excellent verbal and written communication skills
- Motivated, self-directed and work effectively both independently and in a team environment
- Proven technical leadership, including: mentoring others, driving methodologies – Advantage