The world is transforming and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. If you are excited about advanced development of breakthrough technologies for future-generation Efficient CPU cores, we invite you to join us to do something wonderful.
As a CPU Design Verification Engineer in the E-Core group you will:
Understand Power management flows and its integration into cluster level. Knowledge of Intel power flow is plus.
Develops pre Silicon design verification tests to verify design requirements at BUS cluster.
Creates test plan, directed/random templates, develop checkers and monitors in UVM, and finding and implementing corrective measures for failing RTL tests.
Analyzes and uses results to modify testing.
The Pre-Si Validation Engineer should possess the following attributes.
Excellent problem-solving skills and the ability to communicate within the team
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have master's in electrical/computer engineering with 3+ years' experience or bachelor's in electrical/computer engineering with 4+ years' experience.
3+ years' experience or familiarity in all of the following:
Scripting languages such as Python and Perl
Computer-architecture familiarity with coherency
Understanding of Power management flows including low power entry/exit, frequency change flows etc
Design verification and validation methodologies with UVM, System Verilog and industry standard EDA tools
Preferred Qualifications (How to Stand out):
Experience with Pre-silicon verification, SoC validation
Proficiency with UVM and C/C++
System Verilog coding and debug
Experience with RTL development
Knowledge of system level boot flows and power management