Senior IP Design Verification Engineer
The Foundational Security team (FST) is looking for logic validation engineers keen to work on a scalable IP design. Candidate will be responsible for the validation of new IP roadmap features as part of FST's HW IP developing HW security for various market segments across Intel.
As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution. Candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, architects and other team members in determining the proper implementation strategy for new design, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC. They will have an opportunity to learn and contribute towards making Intel Hardware more secure.
- Strong analysis, debugging skills, and creative in problem solving.
- Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having passion for design or validation.
- Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up w/ paradigm shift solutions to critical design/validation challenges.
The candidate must possess a minimum of bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent with 5 years of experience or Master's degree in Microelectronics along 3+ years of relevant experience .
- Experience to be considered but not limited:
OVM / UVM
Capable in developing testplans, tests and verification environment based on High Level Architecture specifications.
Coverage-based random constraint simulation
Object-Oriented Programming (OOP)
- Advanced English level
- Costa Rican unrestricted work permit
- Scripting (Python/Perl/Shell)
- RTL simulators
- RTL model build
- Interactive debugger
- Power-aware simulation
- Power management, IOSF, AHB, PCI express or any industry standard BUS protocol