Senior Logic Design Engineer
We are looking for highly passionate new talents to work on industry leading DDR PHY design as Senior Logic Design Engineer. You will be contributing to Intel family of products on the latest process and create the world-changing technology. You will be responsible for:
Internal IP RTL design/development
Define and implement new features, change requests and improvements on existing features for the IP.
Drive and ensure IP handoff quality assurance and compliance.
Define power intent strategy, handling of signals crossing power planes and clock domains; along with other FE collateral for integration.
Perform design exercises, collaborate with verification and structural design teams for functional/feature/integration validation and physical design implementation.
Perform FE Quality checks in various logic design aspect ranging from RTL static checks to RTL synthesizability check, timing/power convergence, netlist quality check, Formal Equivalent Verification and many more
Candidates should have a minimum of a Bachelor or Master Degree in Electrical and Electronic or Computer Science Engineering, and at least 5 years relevant working experience.
Knowledge in one or more of the following domains:
IP/Subsystem architecture, I/O architecture, industry standard high speed bus protocols
Industry exposure and knowledge of design methodology
Proficient in RTL design using Verilog/System Verilog
Knowledge in industry FE/RTL tools and design methodologies
Knowledge in JEDEC and DDR design would be an advantage