SoC Design Engineer

Intel

Posted Feb. 12, 2024

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Job Description


Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IP to SoC handoff.

Qualifications


You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.


Minimum Qualifications:
Bachelor degree in Electronic, Electrical, Mechatronic engineer, computer science, or related field of study.

At least 1 year of experience in:
- Python or similar programming language, packages, classes, methods and properties
- Unix/Linux and Windows operating systems
- VLSI design (Relevant experience can be obtained through schoolwork, classes and project work, internships, and/or work experience)

- Intermediate English Level.
-Costa Rican unrestricted work permit.


Preferred Qualifications:

Major EDA tools (e.g., Synopsys VCS/Fusion Compiler/Spyglass, Cadence - Conformal/Xcelium, Siemens Mentor Graphics Tessent, etc.)
Knowledge in any of the next areas is a plus:
System Verilog / OOP, OVM/UVM.
IP-level design and/or verification.
SOC-level design/integration and/or validation.
RTL quality checks.
Simulation-based debug (VCS, Verdi, DVE).
Computer (CPU) and/or System (Platform) Architecture.
Emulation at SoC and/or Platform level.
Firmware and/or boot development/debug.
Object Oriented programming.
Front-end Design TFMs (Tools, Flows, and Methodologies).


Inside this Business Group


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.