SOC Logic Design Engineer
IFS (CDE) Customer Design Enablement team is looking for a dynamic engineer who can design/validate high speed digital interfaces like UCIe, LPDDR, PCIe, Protocol bridges (AXI/CFI/APB/PSF), NOC, HBI, FDI, etc ... and collaborate with internal teams, document micro-architecture and implement the design using System Verilog. In this role you will be actively involved in the hardware modelling and simulations, random and focused stimulus generation and coverage.
Job responsibilities include but are not limited to:
Microarchitecture 3DIC design configuration and die partition for SoC or Subsystem development.
Work on RTL coding, logic design.
Run, analyze and fix various quality check tools and flows such as VCLP, FEV, CDC and Lint, etc.
Define power domains using UPF and hit performance, power and area targets.
Participate in timing closure to work with backend engineers on pre and post physical design.
Participate in validation to work with verification engineers to debug test cases in RTL and Gate Level simulation environment.
Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.
Bachelor's degree in Computer Engineering, Electrical Engineering, or equivalent with Master's degree in Computer Engineering, Electrical Engineering.
3+ years of industry experience listed below.
Expertise in Verilog/System Verilog, Lint/CDC/Synthesis/STA/Formal Equivalent Verification, etc.
Digital design or Computer architecture, or Object-Oriented Programming (OOP), or Design verification System Verilog OVM/UVM.
Knowledge in ASIC validation methodology, Verilog testbenches, UVM and RAL.
Experience in simulation/debug tools: VCS, Verdi.
Demonstrate excellent communication, leadership and teamwork skills.
Knowledge in Unix shell, Python and Perl scripting.
Knowledge in Design For Test (DFT), synthesis and APR tools.