SoC Power Management RTL Design Engineer
Job DescriptionIf you are passionate about computer graphics and working with leading graphics engineers on Intel's latest GPU/CPU architecture, then our Client GFX and AI Graphics Engineering (CGAI) Team has opportunities for you. Client GFX and AI Graphics Engineering (CGAI) is responsible for delivering industry-leading GPU (3D, media, compute, and display) hardware intellectual property (IP) blocks and system-on-chip (SoC) products for discrete graphics and throughput computing. We strive to lead the industry through continuous innovation and world-class engineering. The Discrete Graphics SoC team is within CGAI and we charter/responsible for improving the energy efficiency of our Xe GPUs. As a member of Power Management team, you will be prototyping low-power solutions for various design blocks. You will be collaborating with architects, RTL and Platform, and software teams to analyze and implement low-power solutions for next generation Intel GPU products. We work closely with partners across Intel and we are looking for a SoC Design Engineer to join our team. In this position you will help us with the following responsibilities: � Participate in the development of Architecture and Microarchitecture specifications for SOC Level Clocking, Reset and/or Power Management features � Define and implement new features in RTL at IP or SOC level � Collaborate with cross-functional teams (FW, Validation, SD, SV, etc.) to make sure designs are delivered on time and with highest quality Closely work with Verification team and help define testplan and debug design. Participate and drive timing convergence for high speed designs including micro-architecture optimizations Experience with design tools and flows such as Lint, CDC/RDC, UPF/VCLP
Minimum skills and experience that will get you notice:
You must possess a minimum of Bachelor Degree in Computer Engineering, Computer Science or Electrical Engineering with 7+ years of industry experience. Or a Master with 5 + years.
Your experience should be in the following:
� High performance digital logic designs and integration
� SOC architecture, design flows and debug skills
� Experience in SoC Power Management, Low Power design.
� RTL design using Verilog/System Verilog
Strong experience with Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State Machines
Strong knowledge of digital design involving multiple clock domains and power management.
Knowledge of low power design, tools and methodologies. Power intent UPF specifications knowledge a plus.
Behavioral traits that we are looking for:
� Good communication and collaboration skills.
� Possess strong teamwork, problem-solving and influencing skills along with abilities to work with different geographical locations
� Ability to work independently and proactively to lead technical activities