SOC SD Physical Design Engineer


Posted Feb. 12, 2024

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Job Description

Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPUspecific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.


You should possess a Master's degree in EE with at least 6-10 years of experience or a Bachelor's degree in EE with at least 8 years of experience in VLSI physical design. Additional qualifications include: Knowledge of microelectronic designs, semiconductor device physics, CMOS process and physical layout. Good understanding of complete Physical design flow.Hands-on experience in converging complex blocks from RTL to GDSII (more than 500K instances) with embedded macros and low power implementation. Experience with PCIE or LPDDR phy integration is an add-on. Tape out experience with good understanding of latest process nodes DRC's (10nm, 7m/5nm). Experience in automation for design methodology and flow development. Strong debugging skills is must and should come up with technical solutions independently. Experience in logic synthesis, timing constraint development, floorplan, power plan, CTS, routing and timing closure and DRC and LVS closure.Experience in backend verification flows like STA, FEV, IR-drop analysis and low power verification.Good hands-on knowledge on EDA tools like Synopsys FC/DC-ICC2, Primetime, Spyglass, Cadence LEC, Ansys Redhawk and Calibre Drv/ICWEBV2.Good knowledge in scripting languages like Tcl and Shell (csh/tcsh/bash). Hands-on Experience in developing utilities in TCL/TK. Familiarity with hardware description language such as Verilog or System Verilog.Must be a good team player. Efficient in working with cross functional/geo teams with strong communication and leadership skills.

Inside this Business Group

The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center.  Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.

Other Locations

IN, Hyderabad

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at and not fall prey to unscrupulous elements.

Working Model

This role will require an on-site presence.