Staff SoC Physical Design Engineer
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimizes design to improve productlevel parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 5 years of experience in SOC/Analog/IP/ASIC design and/or methodology development.
Minimum 3 years of experience in writing and producing software code using languages such as PERL and TCL.
Minimum 5 years of experience in using Synthesis, Place and Route physical design tools and flow, with demonstrated experience in fixing timing, low power, IR drop, layout DRC violations, and successful tape-out of designs in advanced nodes.
Experience in Unix/Linux and shell programming.
Experience in 3DIC design will be an added advantage.