Staff/Senior Staff Design Verification Engineer
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.
Possess at least a degree in Electronics Engineering, Computer Engineering, Computer Science, or equivalent and experience with IP/SoC design or verification development.
Bachelors with at least 7 years' experience OR
Masters with at least 5 years' experience OR
Doctorate with at least 3 years' experience.
Strong technical leader who communicates well with great influencing skills.
Strong analysis, debugging skills, and creative in problem solving.
Motivated, Self-driven and Independent
Someone who wants to make a difference through technology while having FUN.
Additional Qualifications (EVEN BETTER):
Experience in any of these design tools and methodologies:
- System Verilog (OVM/UVM)
- Scripting (Python/Perl/Shell)
- Experience in PCI Express, USBX, USB4 or any standard HSSIO protocol would be added value
- RTL simulators
- Interactive debugger
- RTL model build
- Testbench development
- Power-aware simulation
- Coverage-based random constraint simulation.
Experience in any of these areas:
- Power Management
- Design For Test/Verification (DFT/DFV/DFX)
- Any industry standard device OR interface protocol.