Technology Development Test Chip Logic/RTL Design Engineer

Intel

Posted Feb. 12, 2024

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Job Description


The IP Test chip and Validation Engineering team is hiring experienced Logic Design Engineer.

You will be responsible for, but not limited to:

- Work with a high performing team to deliver fully functional test chips on Intel's latest process technology.

- Reduce Product risk for various Foundational IPs including Memory Compilers, Standard Cells, PLLs, Digital Thermal Sensor, GPIOs, etc.

- Create or understand logic functionalities in terms of block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.

- Implement RTL in System Verilog, perform unit level testing, debug tests, SDC and UFP generation.

- Integrate hard IP and soft IPs including industry standard and proprietary interfaces.

- Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis.

- Ensure designs are delivered on time and with the highest quality by using proper checks.

- Resolve technical issues in developing digital blocks, gate level simulation, power, and static timing analysis with team members.- Work with verification team for test plan/strategy to meet all functional requirements and performance.

- Work with timing and physical team for timing closure and meet power and area goals.

- Support project managers with effort estimations and resource planning.

- Support team leader in coaching, training and development team members.

In addition to the qualifications a successful candidate will demonstrate:

- Understanding of common interfaces.

- Integration knowledge of analog circuits and mixed signal designs.

- Knowledge of different design styles and tradeoffs.

- Analytical and communication skills in both written and verbal.

#DesignEnablement


Qualifications


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.


Minimum Qualifications:


Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or related field.

3+ years of experience in the following:


-  RTL coding and/or IP integration experience.
- Interfacing with IP teams.

Preferred Qualifications:


3+ years of experience in the following:

- Auto P and R, Primetime, System C/Verilog, post-silicon testing, etc


Inside this Business Group


IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.