ASIC Silicon Design Engineer

Advanced Micro Devices Inc

Santa Clara, California, United States

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

ASIC Silicon Design Engineer

THE ROLE:
Come join a world-class ASIC team that has developed over 30 production ASICs over the last 20 years covering the areas of networking, storage, and compute applications. We are hiring ASIC engineers to
help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain-specific processors for the IAAS and smart-switch
markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and
security virtualization services for both the public and private cloud markets. Come join our growing team and make your mark in the fast-growing cloud computing industry!
You will participate in the HDL design of hardware modules included in high performance Pensando-developed P4 processor pipelines, packet switches, programmable DMA engines, offload accelerators, PCIe and Ethernet interfaces, DDR4/DDR5 memory controllers, high bandwidth
network-on-chip interconnects, memory caches, and ARM processor subsystems.
You will utilize your digital design and system verilog HDL skills to contribute to modules that constitute the micro-architecture of our ASIC products.

In this role, you will be collaborating closely with your teammates in design and architecture and be responsible for defining module-level micro-architecture including interfaces, register definitions, and hardware implementation of control and data paths. You will participate in design reviews as well as contribute to design verification test plan reviews and debug. Your design and debug skills will be leveraged across module-level, full-chip, emulation, prototyping, silicon bring-up, manufacturing
diagnostics, compilers, and shipping platform software.

KEY REQUIREMENTS:

● Verilog , System Verilog , VHDL, Perl/Python, C or C++
● Synthesis, Spyglass/Lint, Power optimization, CDC, LEC
● System Verilog simulators and waveform debuggers
● Accelerators/Emulation/ FPGA prototyping is a plus
Design experience:
● Developing Microarchitecture and Verilog RTL
● Reviewing Synthesis, Timing, Spyglass/Lint Reports and fix the RTL
● Help develop and review the test plans, tests and coverage reports to create a robust tape-out
Domain knowledge:
● Experience with design and algorithms of parser
● Experience with design and development of peripherals and storage devices
● Experience with integration of external IPs for SOC subsystems
● Experience with high speed IO, e.g. DDR / Ethernet, etc.
● Experience with processor ISA is a plus
● Experience with network protocols, e.g. L2 / L3, etc., is a plus
● Be well versed in interface timing budget & clock domain crossing design
● Working knowledge of timing and debug from the ASIC through the board to peripherals

Other qualifications:
● Solid knowledge and understanding of Computer Architecture
● Passionate and analytic with excellent technical problem-solving skills
● Ability to manage multiple tasks and work toward long-term goals
● Excellent communication skills (verbal and written)

KEY RESPONSIBILITIES:
You will be responsible for designing and owning the RTL codes of 1 or more crypto blocks, debugging
the simulation tests, solving any physical design issues related to timing / congestion / CDC etc., and
validating the block(s) on emulator and on silicon.
.
PREFERRED EXPERIENCE:
8+ years and MS
10+ years and BS

ACADEMIC CREDENTIALS:
BSEE or equivalent. MSEE preferred

LOCATION:
San Jose, CA

#LI-LM1

At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

ASIC Silicon Design Engineer

ACADEMIC CREDENTIALS:
BSEE or equivalent. MSEE preferred

LOCATION:
San Jose, CA

#LI-LM1