Front-End Design Verification Methodology Engineer
Advanced Micro Devices Inc
Santa Clara, California, United States
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WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
The focus of this role is to R&D planning, building, and executing methodology for hardware design integration and design verification of new and existing features for AMD’s designs, resulting in no bugs in the final deliverable.
THE PERSON:
You have a passion for modern, complex hardware architecture, digital design, design integration and design verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, firmware engineers and others as relevant to understand new features to be designed and verified and new design verification flows to be created
- Play a key role in coming up with next-gen solutions to DV flow problems for cutting edge AMD designs
- Debug design integration flow or design verification flow failures to determine the root causes; work with RTL, verification and firmware engineers to resolve design flow defects and correct issues
- Be a go-to person for providing solutions to a large group of engineers using flows that you provide
PREFERRED EXPERIENCE & SKILLS:
- General coding skills and familiarity
- Quick learner for programming languages with excellent coding & debugging skills
- Programming languages – C/C++, Ruby, Perl, Python, shell scripting, Makefile
- Good understanding of basic computer architecture.
- Data formats like XML, JSON, YAML
- Linux/Unix OS, commands, and working with the file system
- String processing and regular expressions
- Version control system like perforce, git, etc
- Familiarity with Linux OS and shell scripting
- Debugging skills
- Design Build
- Quick learner for new build systems and framework
- Build performance analysis/debugging
- Strong in Makefile based build environment
- Good knack for finding inefficiencies in a build system and user build code. Including hardware (processor and disk) and NFS related latency related build performance issues
- Design Verification Methodology
- Familiarity with front end design and verification flows in a silicon/EDA company
- Knowledge and Experience with Verilog, VHDL, System Verilog, UPF, IPXAC
- EDA Toolset: VCS, VCS NLP, VC LP, VC Formal, Mentor in CDC, SpyGlass-CDC, Formality, Synopsys Core tools
- Debugging of functional simulation failures.
- Job management systems like LSF
- Soft skills
- Person who will interact with multiple teams from multiple geographies
- Familiar with working and collaborating across teams in different AMD locations
- Must have great communication skills and the ability and desire to foster a team environment
ACADEMIC CREDENTIALS:
- B Tech/M Tech/BE/ME/PhD in Computer Sci/Electronics & Communication/IT or Equivalent
- Prior work experience with EDA companies or Methodology teams in semiconductor design majors is a plus
LOCATION:
- Santa Clara, CA
#LI-G11
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
The focus of this role is to R&D planning, building, and executing methodology for hardware design integration and design verification of new and existing features for AMD’s designs, resulting in no bugs in the final deliverable.
THE PERSON:
You have a passion for modern, complex hardware architecture, digital design, design integration and design verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, firmware engineers and others as relevant to understand new features to be designed and verified and new design verification flows to be created
- Play a key role in coming up with next-gen solutions to DV flow problems for cutting edge AMD designs
- Debug design integration flow or design verification flow failures to determine the root causes; work with RTL, verification and firmware engineers to resolve design flow defects and correct issues
- Be a go-to person for providing solutions to a large group of engineers using flows that you provide
PREFERRED EXPERIENCE & SKILLS:
- General coding skills and familiarity
- Quick learner for programming languages with excellent coding & debugging skills
- Programming languages – C/C++, Ruby, Perl, Python, shell scripting, Makefile
- Good understanding of basic computer architecture.
- Data formats like XML, JSON, YAML
- Linux/Unix OS, commands, and working with the file system
- String processing and regular expressions
- Version control system like perforce, git, etc
- Familiarity with Linux OS and shell scripting
- Debugging skills
- Design Build
- Quick learner for new build systems and framework
- Build performance analysis/debugging
- Strong in Makefile based build environment
- Good knack for finding inefficiencies in a build system and user build code. Including hardware (processor and disk) and NFS related latency related build performance issues
- Design Verification Methodology
- Familiarity with front end design and verification flows in a silicon/EDA company
- Knowledge and Experience with Verilog, VHDL, System Verilog, UPF, IPXAC
- EDA Toolset: VCS, VCS NLP, VC LP, VC Formal, Mentor in CDC, SpyGlass-CDC, Formality, Synopsys Core tools
- Debugging of functional simulation failures.
- Job management systems like LSF
- Soft skills
- Person who will interact with multiple teams from multiple geographies
- Familiar with working and collaborating across teams in different AMD locations
- Must have great communication skills and the ability and desire to foster a team environment
ACADEMIC CREDENTIALS:
- B Tech/M Tech/BE/ME/PhD in Computer Sci/Electronics & Communication/IT or Equivalent
- Prior work experience with EDA companies or Methodology teams in semiconductor design majors is a plus
LOCATION:
- Santa Clara, CA
#LI-G11