Graduate - ENGINEER

Infineon Technologies

Verilog System Verilog RTL

Posted May 13, 2023

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Are you looking to gain Internship experience in a dynamic organization and want to be part of something exciting and unique? If you are ready to be part of the digital revolution that is shaping our world then please join us. #AmericasGraduates
In your new role you will:

• Define and Implement Verification plan, write tests and debug failures
• Participate in team activities such as verification infrastructure improvements
• Motivated to work with different verification methodologies including UVM
• Document results and generate status reports
• Actively participate in cross functional collaboration with design teams

• Master's degree in electrical Engineering and 0-1 years of work experience or Bachelor's degree and 1-3 years of work experience
• Basic know-how of verification infrastructure such as simulation test bench, coverage, assertions
• Basic knowledge of digital and/or mixed-signal design, able to read and debug RTL designs
• Understanding of verification methodologies such as UVM, OVM, System Verilog is a plus
• Knowledge of C, Python, Tcl, Perl etc. for developing test content and scripts