MTS Verification Engineer
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MTS VERIFICATION ENGINEER
THE ROLE:
AMD is adding to its wireless silicon and IP design verification team. This is a fantastic opportunity for Electronic Engineers with a passion for FPGA or ASIC verification methodology to join a team with access to world-class development infrastructure and specialise on this key aspect of the FPGA development cycle. You'll be working in a team responsible for wireless silicon and soft IP components and systems for use by the world’s leading wireless telecommunications companies.
THE PERSON:
You have a passion for delivering high quality HDL designs and a broad exposure to the verification methodology techniques required to achieve this.
You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
In this role you will be working on all stages of verification, including:
- Deriving verification specifications from customer requirements/industry standards and collaborating with team members to extract the features to be verified
- Verification planning, testbench architecture design and development
- Estimating the time required to write the new feature tests and any required changes to the test environment
- Building the directed and random verification tests
- Debugging test failures to determine the root cause; working with RTL engineers to resolve design defects and correct any test issues
- Reviewing functional and code coverage metrics
- Modifying/adding tests or constraining random tests to meet the coverage requirements
- IP product verification
You will be using tools and techniques, such as Random-Constrained Functional-Coverage driven UVM testbenches. The role may also involve integrating IP models into verification environments, writing assertions/properties (SVA), scripting tool flows, and verification of IP developed in high-level languages.
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC or FPGA verification
- Proficient in debugging RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with System Verilog, C/C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Python, Makefile
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS VERIFICATION ENGINEER
THE ROLE:
AMD is adding to its wireless silicon and IP design verification team. This is a fantastic opportunity for Electronic Engineers with a passion for FPGA or ASIC verification methodology to join a team with access to world-class development infrastructure and specialise on this key aspect of the FPGA development cycle. You'll be working in a team responsible for wireless silicon and soft IP components and systems for use by the world’s leading wireless telecommunications companies.
THE PERSON:
You have a passion for delivering high quality HDL designs and a broad exposure to the verification methodology techniques required to achieve this.
You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
In this role you will be working on all stages of verification, including:
- Deriving verification specifications from customer requirements/industry standards and collaborating with team members to extract the features to be verified
- Verification planning, testbench architecture design and development
- Estimating the time required to write the new feature tests and any required changes to the test environment
- Building the directed and random verification tests
- Debugging test failures to determine the root cause; working with RTL engineers to resolve design defects and correct any test issues
- Reviewing functional and code coverage metrics
- Modifying/adding tests or constraining random tests to meet the coverage requirements
- IP product verification
You will be using tools and techniques, such as Random-Constrained Functional-Coverage driven UVM testbenches. The role may also involve integrating IP models into verification environments, writing assertions/properties (SVA), scripting tool flows, and verification of IP developed in high-level languages.
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC or FPGA verification
- Proficient in debugging RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with System Verilog, C/C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Python, Makefile
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid