Principal Design Architect (f/m/div)*
Are you passionate about Digital IC Design? Do you use your creative mindset to achieve innovative solutions? In our Design Center in Padova some of the best experts in the industry are developing leading edge technology for tomorrow’s Automotive products. Join our motivated team as Principal Design Architect and find the perfect environment to achieve success!
As a Principal Design Architect, you will be responsible to drive and/or support product feasibility studies and product architecture cooperating with Application, Analog Design and Technical Marketing Engineering teams.
In your new role you will:
- Define top level concept partitioning and interfaces definition of digital and analog-mixed signal blocks;
- Define DFT concept and integration system architecture;
- RTL design (SystemVerilog) and design constrains providing documented compliance to performance and quality requirements;
- Support R2G flow and activities guaranteeing RTL code synthesis feasibility;
- Generate Design Documentation Reports and participate to Design Reviews;
- Drive and/or support risk assessment, risk management and Design/Product FMEAs;
- Drive and/or support preparation of product level verification and validation plans as well as work with test engineers in defining the product test plan;
- Support product validation and debug activities working with Product, Quality and Test engineering up to production ramp-up;
- Contribute to Technology Process and Design Methodology improvements.
You are best equipped for this task if you have:
- A Master Degree or PhD in Electrical/Electronic Engineering or equivalent degree with specific knowledge of microelectronic devices and related digital circuit design;
- At least 7+ years of digital design and semicustom flow experience on sub-micron technologies;
- Solid knowledge of hardware description language; System Verilog is a plus;
- Experience in defining ARM-CortexM based architectures;
- Good knowledge of analog & mixed signal IC architectures and integration requirements;
- Good experience with common design tools;
- Good knowledge of Unix OS and scripting languages (Perl, Python);
- Proficient experience using simulation on RTL and gate-level, synthesis, equivalence checking, CDC; UVM methodology knowledge is a plus;
- DFT experience would be a plus;
- Experience in complete RTL to GDS flow is a plus;
- Knowledge of Requirements Management methodologies is a plus;
- Fluent English, Italian appreciated, German would be a plus.
Please send us your CV in English.