Do you want to be part of the growth of our R&D Center in Padova? Do you want to technically lead a digital verification team and play a crucial role at the #1 semiconductor partner in the fast-changing Automotive world? Then, you cannot miss this opportunity to join Infineon’s success story! Apply now to become a Principal Engineer for Digital Verification.
As a Principal Engineer in Digital Verification, you will be responsible for technically leading a digital verification team in projects that contribute to technological progress in the automotive area.

In your new role you will:

• Be responsible for the technical coordination of the digital verification team related to ongoing projects;
• Create verification plans and test suites based on design specifications;
• Build verification environments consisting of test benches for top/block level;
• Design self-checking test benches using verification techniques based on SystemVerilog and UVM methodology;
• Implement functional coverage and assertions using SystemVerilog;
• Develop test and functional coverage plans based on device specifications;
• Be responsible for analyzing and debugging simulation failures;
• Make regression simulation while analyzing functional coverage and performance results.

High-quality standards are part of your daily life. You act fast and strive for continuous improvement. You are a problem solver with great analytical skills. Furthermore, you have a collaborative, result-oriented and proactive mindset aligned with your good communication skills.

You are best equipped for this role if you have:

• A Master Degree or PhD in Electronic Engineering or similar field of studies with specific knowledge of microelectronic devices and related digital circuit design;
• Solid experience in digital design implemented on sub-micron technologies;
• At least 3 years of Power Management ICs (PMICs) experience in automotive;
• At least 5 years of experience as a Technical Lead or Mentor;
• Solid UVM experience of at least 8 years;
• Experience in Power-aware verification using UPF/CPF;
• Solid knowledge of VManager and VPlanner;
• Experience with automotive standards in particular with ISO26262 and requirements-driven simulation;
• In-depth knowledge of Unix OS and scripting languages, such as Perl and Python;
• Fluency in English (mandatory).

It is an advantage if you have:

• Knowledge of analog & mixed-signal IC architectures and integration requirements;
• Knowledge of Jama and Jira;
• Knowledge of Requirements Management methodologies;

Although solid experience as a Principal Engineer is desired, we welcome applications from senior and junior candidates as we have a team ready to support your development.

Please send us your CV in English.