Senior Digital Design Engineer
Intel
Leixlip, , IE
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Job Description
Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us-and help us create the next generation of technologies that will shape the future for decades to come.
In this position you will be a member of the silicon engineering division of the NEX Cloud Network Group. As part of this high-performance team, you will be involved in the digital design of leading edge Cryptographic, Ethernet and Packet Processing solutions on best in class ethernet products. The team is looking to hire engineers with RTL development experience to augment and provide technical leadership within the existing team. Experience in adjacent engineering disciplines such as software development would also be considered.
Leixlip is the primary location for this position, however, we offer flexibility to work from other Intel sites like Shannon. In addition we are happy to facilitate arrangements which facilitate a Home Office set up, from a work/life balance perspective.
Your responsibilities will include but not be limited to:
Developing the micro-architectural specification of complex design block(s).
Logic implementation of complex design block(s) using RTL coding techniques.Working with pre-Silicon validation engineers to develop cluster level directed/random tests and environments
Working with the Physical Design (Layout) team on Synthesis, Formal Verification and Timing Convergence
Interacting closely with other teams such as the Architecture, DFx, Software, Firmware and Post-Silicon Validation
Technical team leading including mentoring and directing junior engineers in their tasks.
Qualifications
Educational Qualifications:
At minimum an Honours degree (level 8 on www.nfq.ie) in Electronic Engineering, Computer Science or equivalent.
Required Experience:
6+ years of RTL level Digital IC Design experience using System Verilog and/or Verilog.
Strong ASIC, SoC or FPGA design experience.
Proven track record of successful first time delivery of projects.
A self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Experience with industry standard development tools and methodologies.
Previous practical experience of leading technical design teams and directing junior engineers.
Preferred Experience:
Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.
Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS*, PrimeTime, Design Compiler, Jasper (FPV).
Experience with high speed I/O such as PCI Express and Gigabit Ethernet.
Experience with switching/routing and communications protocols such as Ethernet