Senior Engineer Systems Engineering
Penang (Malaysia), , MalaysiaApply Now!
- Work with an experienced engineer and develop memory sub system based on AHB or AXI interconnect protocol using Verilog/System Verilog
- Work with an experienced engineer and develop high speed serial interfaces with SDR and DDR protocol using FPGA resources
- Follow a test plan, develop Verilog or C based test case, execute and report test results
- Maintain simulation env based on Verilog and C, perform modification based on change in requirements, target device RTL etc.
- Participate in continuous improvement process and leverage the capabilities of the latest FPGA technology to ensure quality and faster time to market
- Knowledge on embedded system with ARM CPU
- Knowledge on Verilog RTL design, verification, coverage analysis
- Knowledge on C or similar low-level programming language
- Experience with regression test bench & test suit development, debug
- Knowledge on Xilinx or Altera based FGPA design, implementation, and testing.
- Experience with design methodology tools such as (or equivalent) Vivado, Questa, Oscilloscope, Logic Analyzer
- Able to write synthesizable RTL, integrate hard IP, Soft IP and create FPGA based design
- Must have strong teamwork and communication skills, passion, productivity, and self-learning ability