Silicon Design Engineer 2
Advanced Micro Devices Inc
San Jose, California, United States
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WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE PERSON
We are looking for a RTL digital design engineer to join the FPGA Architecture Development group. The right candidate will focus on full-chip RTL development and integration for next generation FPGA and programmable SoC products. The candidate must be able to work with team members in globally diverse regions.
THE ROLE
Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying that full chip models match architectural intent. Developing custom tools and methodologies to improve development efficiency and quality
KEY RESPONSIBILITIES:
- Strong problem solving and critical thinking skills
- Ability to work within a dynamic cross-functional team environment across globally diverse regions
- Positive attitude and strong personal desire to 'make a difference'
- Self-starter demonstrating an ability to work on own as well as ability to work within a team
- Meticulous and able to work with minimum supervision
- Good communication and presentations skills, and follow through
PREFFERED EXPERIENCES:
- 0-2 years of experience using FPGAs and understanding FPGA architectures
- 0-2 years of experience with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.)
- Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog
- Good waveform debug skills using front end industry standard design tools like VCS, NC Sim, or Verdi
- Knowledge of Unix/Linux environment and scripting languages such as Perl or Python
- Some Experience using Revision Control tools – CVS, Subversion, or Perforce
ACADEMIC CREDENTIALS:
- Bachelor degree in Electrical Engineering or equivalent qualifications, advanced Degree a plus
#LI-JY1
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE PERSON
We are looking for a RTL digital design engineer to join the FPGA Architecture Development group. The right candidate will focus on full-chip RTL development and integration for next generation FPGA and programmable SoC products. The candidate must be able to work with team members in globally diverse regions.
THE ROLE
Building full-chip RTL connectivity models. Integrating RTL components from multiple design teams. Verifying that full chip models match architectural intent. Developing custom tools and methodologies to improve development efficiency and quality
KEY RESPONSIBILITIES:
- Strong problem solving and critical thinking skills
- Ability to work within a dynamic cross-functional team environment across globally diverse regions
- Positive attitude and strong personal desire to 'make a difference'
- Self-starter demonstrating an ability to work on own as well as ability to work within a team
- Meticulous and able to work with minimum supervision
- Good communication and presentations skills, and follow through
PREFFERED EXPERIENCES:
- 0-2 years of experience using FPGAs and understanding FPGA architectures
- 0-2 years of experience with stages in the ASIC design flow including verification methodologies and tools (UVM/OVM, Formal Checks, Lint tools, etc.)
- Knowledge in RTL and behavioral coding, preferably with Verilog and SystemVerilog
- Good waveform debug skills using front end industry standard design tools like VCS, NC Sim, or Verdi
- Knowledge of Unix/Linux environment and scripting languages such as Perl or Python
- Some Experience using Revision Control tools – CVS, Subversion, or Perforce
ACADEMIC CREDENTIALS:
- Bachelor degree in Electrical Engineering or equivalent qualifications, advanced Degree a plus
#LI-JY1