Silicon Design Engineer 2
Advanced Micro Devices Inc
San Jose, California, United States
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WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
As a member of the SoC Design and Integration timing team, you will work collaboratively with various IP teams to execute, design integration tasks in the role of a STA timing engineer for high quality SOCs
THE PERSON:
- As a STA Engineer in the integration team, you will have responsibilities spanning various aspects of SOC design:
- Full chip and sub full chip level timing closure/signoff activities throughout the entire project cycle.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Work on AMD SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.
- Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
KEY RESPONSIBILITIES:
- Own key full chip timing activities, deliver timing and noise signoff meeting the defined requirements
- Responsible for defining and implementing interface timing coverage. Coordinate and work closely with various engineering groups, including frontend design, CAD, physical design and device software modeling
- Responsible for deriving ECOs for necessary timing and noise fixes leading to full chip timing closure for the targeted block interfaces
- Participate in methodology development related to block level and chip level timing signoff.
- Define and Implement the necessary automation to facilitate timing closure setup and analysis, data manipulation, results summary, timing and noise violation debugging, and ECO generations
PREFFERED QUALIFICATIONS:
- Minimum 1-3 years experience
- In depth working knowledge of Static Timing Analysis tools and flows, (Prime Time tool suite)
- Basic knowledge of FPGA architecture
- Proficiency in automation scripting in Perl, TCL, or Python
- Working knowledge of ASIC Design timing closure, methodology and analysis techniques
- Knowledge in ASIC timing constraints/SDC generation and management
- Timing debugging skills
- Good verbal and written communication and presentation skills
PREFERRED ACADEMIC COURSES:
- Digital Logic Design
- Computer Architecture
- CMOS Design
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering or related equivalent degree
#LI-JY1
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
As a member of the SoC Design and Integration timing team, you will work collaboratively with various IP teams to execute, design integration tasks in the role of a STA timing engineer for high quality SOCs
THE PERSON:
- As a STA Engineer in the integration team, you will have responsibilities spanning various aspects of SOC design:
- Full chip and sub full chip level timing closure/signoff activities throughout the entire project cycle.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Work on AMD SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.
- Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
KEY RESPONSIBILITIES:
- Own key full chip timing activities, deliver timing and noise signoff meeting the defined requirements
- Responsible for defining and implementing interface timing coverage. Coordinate and work closely with various engineering groups, including frontend design, CAD, physical design and device software modeling
- Responsible for deriving ECOs for necessary timing and noise fixes leading to full chip timing closure for the targeted block interfaces
- Participate in methodology development related to block level and chip level timing signoff.
- Define and Implement the necessary automation to facilitate timing closure setup and analysis, data manipulation, results summary, timing and noise violation debugging, and ECO generations
PREFFERED QUALIFICATIONS:
- Minimum 1-3 years experience
- In depth working knowledge of Static Timing Analysis tools and flows, (Prime Time tool suite)
- Basic knowledge of FPGA architecture
- Proficiency in automation scripting in Perl, TCL, or Python
- Working knowledge of ASIC Design timing closure, methodology and analysis techniques
- Knowledge in ASIC timing constraints/SDC generation and management
- Timing debugging skills
- Good verbal and written communication and presentation skills
PREFERRED ACADEMIC COURSES:
- Digital Logic Design
- Computer Architecture
- CMOS Design
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering or related equivalent degree
#LI-JY1