Silicon Design Verification Engineer, Sr. Staff - ASIC, UVM, System Verilog, Networking Protocols, etc.
Advanced Micro Devices Inc
Ottawa, Ontario, Canada
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WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
Are you a driven, inquisitive, and hungry for knowledge mind? AMD is looking for people like you to join the growing ASIC design verification team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON:
You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with design engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, with focus on use cases described in the architecture and design specifications
- Drive the testbench architecture and development of leading edge IP
- Develop directed and constraint random test scenarios as identfied in the test plan
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constraint random tests to meet the coverage requirements
- Push for adoption of best practices in the industry
- Evaluate tools for improving performance and reduce the development cycle
- Propose innovative ways to architect reusable tetbenches
- Offer mentorship to younger team members
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Extensive experience in designing and implementing self-checking testbenches, coverage closure techniques and regression management flows
- Proficient in debugging RTL code using simulation tools
- Proficient working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Hands-on experience with UVM based verification frameworks and testbenches, processes and flows
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
- Experience and knowledge with IEEE security protocols (such as MACsec, IPsec)
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering/computer systems/computer science
LOCATION:
Ottawa, Ontario
#LI-JT1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
Are you a driven, inquisitive, and hungry for knowledge mind? AMD is looking for people like you to join the growing ASIC design verification team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON:
You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Collaborate with design engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, with focus on use cases described in the architecture and design specifications
- Drive the testbench architecture and development of leading edge IP
- Develop directed and constraint random test scenarios as identfied in the test plan
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constraint random tests to meet the coverage requirements
- Push for adoption of best practices in the industry
- Evaluate tools for improving performance and reduce the development cycle
- Propose innovative ways to architect reusable tetbenches
- Offer mentorship to younger team members
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Extensive experience in designing and implementing self-checking testbenches, coverage closure techniques and regression management flows
- Proficient in debugging RTL code using simulation tools
- Proficient working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Hands-on experience with UVM based verification frameworks and testbenches, processes and flows
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
- Experience and knowledge with IEEE security protocols (such as MACsec, IPsec)
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering/computer systems/computer science
LOCATION:
Ottawa, Ontario
#LI-JT1