Silicon Microarchitecture & Logic Design, SOC - Full time


(Taiwan) HsinChu, Taiwan
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Positions are open for full-time positions in the areas of SOC microarchitecture and logic design including on-chip interconnects, caches, high performance memory interface, system control, high-speed IO interfaces, and data parallel processing engine. We are looking for all levels of talent, from new college grads to advanced level of experience. Responsibilities

  • Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
  • Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
  • Validation - support test bench development and simulation for functional and performance verification
  • Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
  • Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power
  • Requirements
  • Thorough knowledge of microprocessor or system architecture in one or more of the following areas: 
  • SOC: Fabric and network-on-chip solutions, high performance system-memory solutions, controllers for high speed I/O like PCI Express, low speed I/O like i2c, Power-management, power delivery, security, and data parallel engines.
  • Knowledge of SystemVerilog
  • Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power microarchitecture techniques
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python
  • Education and Experience
  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.