SMTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
AMD is adding to its Wireless Silicon and IP design verification team. This is a fantastic opportunity for an Engineer with a passion for verification methodologies to join a team with access to world-class development infrastructure. You'll be working in a team responsible for wireless silicon and soft IP components and systems for use by the world’s leading wireless telecommunications companies.
In this role you will be working on all stages of verification, such as deriving specifications from customer requirements and industry standards, verification planning, testbench architecture design and development, coverage closure, and product verification. You will be using modern tools and techniques, such as Random-Constrained Functional-Coverage driven UVM testbenches. The role may also involve integrating IP models into verification environments, writing assertions/properties, scripting tool flows, and verification of IP developed in high-level languages.
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything.
PREFERRED EXPERIENCE:
- BS with 8+ years of exp or MS 6+ years of exp or PhD 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
- Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
- Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
- Good understanding of object oriented programming concepts
- Prior experience in verifying system/sub system level involving multiple blocks
- Prior experience with protocols such as AXI, APB, AHB etc.
- Programming in scripting languages like Python, TCL and Perl
- Excellent communication skills
- Good problem solving skills and analytical ability
- Familiarity with EDA tools for simulation, debugging & coverage analysis
- C or C++ development, or integrating reference models into SystemVerilog/UVM testbenches
- Knowledge of Matlab/Octave, (Tcl/Perl/Python) to control Xilinx tools and/or other EDA tools
- Experience with HW/SW co-simulation tools
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
AMD is adding to its Wireless Silicon and IP design verification team. This is a fantastic opportunity for an Engineer with a passion for verification methodologies to join a team with access to world-class development infrastructure. You'll be working in a team responsible for wireless silicon and soft IP components and systems for use by the world’s leading wireless telecommunications companies.
In this role you will be working on all stages of verification, such as deriving specifications from customer requirements and industry standards, verification planning, testbench architecture design and development, coverage closure, and product verification. You will be using modern tools and techniques, such as Random-Constrained Functional-Coverage driven UVM testbenches. The role may also involve integrating IP models into verification environments, writing assertions/properties, scripting tool flows, and verification of IP developed in high-level languages.
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything.
PREFERRED EXPERIENCE:
- BS with 8+ years of exp or MS 6+ years of exp or PhD 3+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
- Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
- Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
- Good understanding of object oriented programming concepts
- Prior experience in verifying system/sub system level involving multiple blocks
- Prior experience with protocols such as AXI, APB, AHB etc.
- Programming in scripting languages like Python, TCL and Perl
- Excellent communication skills
- Good problem solving skills and analytical ability
- Familiarity with EDA tools for simulation, debugging & coverage analysis
- C or C++ development, or integrating reference models into SystemVerilog/UVM testbenches
- Knowledge of Matlab/Octave, (Tcl/Perl/Python) to control Xilinx tools and/or other EDA tools
- Experience with HW/SW co-simulation tools
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid