Sr. Design Verification Engineer
Advanced Micro Devices Inc
Hyderabad, UNAVAILABLE, India
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Job Description
The individual will manage and contribute to the architecture and implementation of the verification test bench using System Verilog and UVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
KEY RESPONSIBILITIES:
- Collaborate with architects, design engineers, and firmware engineers to understand the new features to be verified
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
Proficient in IP level ASIC Verification.Bachelors or Masters in electrical or computer engineering
- 5 to 10 Years of experience in the SoC Verification / IP Verification / Performance Verification
- Development of Verification Test Plan / Constrained Random Stimulus/ Coverage / Checkers for target design
- Strong experience in development of SV Test Bench for IP's / SoC's
- Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.
- Knowledge of DFT, Reset Flows Verification is a Plus, but not Mandatory.
- Strong analytical problem solving, and attention to details
- Excellent written and verbal communication skills
Excellent interpersonal skills, self-motivated
Education Qualification
- B.Tech / M.Tech with Electronics/Computer Science
#LI-SK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Job Description
The individual will manage and contribute to the architecture and implementation of the verification test bench using System Verilog and UVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.
KEY RESPONSIBILITIES:
- Collaborate with architects, design engineers, and firmware engineers to understand the new features to be verified
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
Proficient in IP level ASIC Verification.Bachelors or Masters in electrical or computer engineering
- 5 to 10 Years of experience in the SoC Verification / IP Verification / Performance Verification
- Development of Verification Test Plan / Constrained Random Stimulus/ Coverage / Checkers for target design
- Strong experience in development of SV Test Bench for IP's / SoC's
- Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.
- Knowledge of DFT, Reset Flows Verification is a Plus, but not Mandatory.
- Strong analytical problem solving, and attention to details
- Excellent written and verbal communication skills
Excellent interpersonal skills, self-motivated
Education Qualification
- B.Tech / M.Tech with Electronics/Computer Science
#LI-SK2