Staff Formal Engineer - System IP
With offices around the world, Arm is a diverse community of dedicated and innovative engineers. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we support our people to share their unique contributions to Arm's success in the global marketplace.
The Budapest System IP team has a track record of numerous successful deliveries, we have an open and relaxed culture where best-in-class, creative engineers work together on significant projects. Our upbeat and collaborative team builds System IP components used in future client, embedded and IoT devices.
At our Budapest-based design center, you will join a hardworking team. You will contribute to the specification, microarchitecture and RTL design of performant, energy efficient and secure IP components.
You will use novel technologies and methodologies to ensure the highest quality products as you collaborate with other Arm engineering teams to build complete IP solutions to address the performance, power and cost requirements for almost all application markets. Join and let's invent the future together!
- You own the verification of one or more non-trivial IP blocks
- You own and develop verification plans, determine the best approach to achieve required quality levels
- You own and develop verification environments (SystemVerilog/UVM, Formal, scripting)
- You handle Verilog RTL logic design and debug; formal bring-up
- You work closely with engineers across design, performance modelling, validation, and implementation to meet all functional requirements, performance, power and area goals
- Propose and prototype new ways and define methodologies to reach goals more efficiently
Required Skills and Experience :
- Master’s degree in Electrical Engineering or Computer Engineering strongly preferred, Bachelor's degree along with shown related experience may be substituted
- Minimum 2 years of post-degree work experience in RTL and microarchitecture design and/or applications development, C++ and assembly development
“Nice To Have” Skills and Experience :
- Experience of block level RTL design and verification for non-trivial FPGA/ASIC developments
- Hands-on experience using Verilog or VHDL HDL for design
- Exposure to all stages of the design cycle: initial concept, specification, implementation and testing, documentation, release and support
- Object oriented software development, object-oriented design patterns
- Hands-on experience of formal verification techniques for rapid IP bring-up
- Designing for synthesis targeted to achieve specified power, frequency, and area targets
- Make good judgements on functionality, performance, and physical implementation trade-offs
- Crafting for synthesis targeted to achieve specified power, frequency, and area targets
- Functionality, performance & physical implementation trade-offs
- Scripting, e.g. with Perl, Python, etc.
- Ability to travel occasionally for training and customer meetings
- Fluency in both written and oral English
All arm employees are provided with vital training to succeed in their respective roles. As well as a friendly and high-performance working environment, Arm offers a competitive benefits package in Hungary including private medical insurance, 25 days of annual leave, sabbatical, supplementary pension, and wellness benefits.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.