Systems IP - Staff/Principal Design Engineer
As part of Arm’s continued growth, the Interconnect team are looking to hire passionate engineers in the Bristol region. Based in an office in Bristol, you will be working on next generation Interconnect products in close collaboration with the Manchester and Sheffield teams. The team is working on a new Arm Corelink Interconnect IP product for Arm, with sophisticated bleeding edge low power, high performance technology.
Would you like to be part of creative, multi-disciplinary, multi-cultural environment, in a role with exciting responsibilities and a chance to create an impact on our industry? We would love to hear from you!
The Interconnect team develops the Arm Corelink Interconnect IP family. This highly scalable IP is designed for intelligently connected AMBA-compliant SoC connectivity, for other performance features including coherency, caches and can be customized for multiple performance points.
Design Engineers are required to have in-depth understanding across all the elements that contribute to the products’ successful delivery, including low-power design techniques, awareness of the impact of design decisions on system performance, ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality cutting edge designs.
- Leading the feasibility analysis of suggested architectures and algorithms to craft creative microarchitecture design solutions and specifications in collaboration with other specialists
- Driving the power measurement and design optimization activities working with stakeholders while tracking the requirements
- Work closely with engineers across performance modelling, validation, and implementation to meet all functional requirements, performance, power and area goals
- Improving design methodology across the System IP group and wider Arm design community
- Providing direction and mentoring to other members of your team as they learn new things and solve complex problems.
Required skills and experience:
- Demonstration of a strong delivery record of high quality, low power, high performance complex micro-architecture and RTL implementations using System Verilog, Verilog or VHDL HDL in reasonable timescales.
- Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices.
- Knowledgeable on ASIC/FPGA design methodology, IP signoff methods with a deep understanding on timing/area/complexity trade-offs for complex data path designs
- Experience of producing specifications and documentation describing complex designs
- Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
‘Nice to have’ Skills and Experience:
- Team leadership and mentoring experience
- CPU or compute subsystem memory micro-architecture
- Working knowledge of SystemVerilog Assertions (SVA) and formal verification
- Knowledge of a scripting language such as Perl, Tcl, C shell
- Knowledge of working with power tools (ex. Power Pro)
- Knowledge of assembly language (preferably ARM), C/C++ and/or hardware verification languages e.g. SystemVerilog