ASIC Bootcode and Firmware Engineer
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THE ROLE:
We are looking for an ASIC BootCode and Firmware Design Engineer to join the Security IP Team. The primary focus of this role is the development and verification of System on Chip secure boot and Security IP initialization embedded firmware. Development of the secure boot and initialization firmware will provide direct and detailed exposure to hardware and software security, cryptography and computer architecture skillsets.
THE PERSON:
The preferred candidate is a self-starter, with a strong interest in SOC and computer architecture and desire to build technical ability in both hardware and software development and verification methodologies and skills. You will also have proven experience in digital hardware verification or embedded software debug.
KEY RESPONSIBILITIES:
Development and verification of embedded firmware for SOC secure boot, SOC initialization and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions.
- Hardware/Firmware co-devlopment in UVM System Verilog and C-DPI structured testbench.
- Hardware/Firmware co-verification in FPGA hardware prototype platform.
- Development of scripts and infrastructure methodologies for the modification, compilation and verification of embedded SOC boot firmware.
- Test plan development and direct participation in the verification and debug of embedded boot firmware functionality. Completion of functional test and code coverage goals.
- Support platform emulation, SOC simulation and silicon bring-up teams.
- Development and modification of the System Verilog and C driven testbench and bus functional models as required.
- Embedded CPU and subcomponent IPs with
- AXI/AHB busses and HW accelerators such as
- Cryptography, Data Compression, DMA, etc.
- Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance models
- Create abstracted FW and HW performance models
- Develop critical target code to collect IP performance key parameters
- Explore subsystem architecture performance trade-off for FW and HW optimization
- Develop and execute subsystem and block level test plans
- Develop FW/HW co-verification methodology
- Develop UVC and System Response models
- Develop and debug UVM and C-DPI test cases with integrated FW
- Improve verification metrics
- Interface with SoC integration and SoC DV teams
- Define and develop IP level DV API to support SoC level DV effort
- Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.
- Support SoC level IP emulation, silicon bring-up and debugging effort
PREFERRED EXPERIENCE:
- ASIC FW and HW design and verification experience
- Prior software development and debug experience
- Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc.)
- Knowledge about UVM methodology and C-DPI methodology
- Excellent knowledge about standard bus/interface protocols (i.e. AXI, AHB, AMBA)
- Excellent experience with firmware design on commercial microprocessors
- Excellent experience with microprocessor tool chain, compiler, assembler, debugger
- Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc.
- Strong analytical/problem solving skills and attention to details
- Being a motivated team member, and able to independently drive tasks to completion as well
- Professional interpersonal and communication skills
ACADEMIC CREDENTIALS:
- Major in Electrical or Computer Engineering.
- Master’s or PhD Degree preferred
LOCATION :
Austin, TX / Folsom , CA
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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
We are looking for an ASIC BootCode and Firmware Design Engineer to join the Security IP Team. The primary focus of this role is the development and verification of System on Chip secure boot and Security IP initialization embedded firmware. Development of the secure boot and initialization firmware will provide direct and detailed exposure to hardware and software security, cryptography and computer architecture skillsets.
THE PERSON:
The preferred candidate is a self-starter, with a strong interest in SOC and computer architecture and desire to build technical ability in both hardware and software development and verification methodologies and skills. You will also have proven experience in digital hardware verification or embedded software debug.
KEY RESPONSIBILITIES:
Development and verification of embedded firmware for SOC secure boot, SOC initialization and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions.
- Hardware/Firmware co-devlopment in UVM System Verilog and C-DPI structured testbench.
- Hardware/Firmware co-verification in FPGA hardware prototype platform.
- Development of scripts and infrastructure methodologies for the modification, compilation and verification of embedded SOC boot firmware.
- Test plan development and direct participation in the verification and debug of embedded boot firmware functionality. Completion of functional test and code coverage goals.
- Support platform emulation, SOC simulation and silicon bring-up teams.
- Development and modification of the System Verilog and C driven testbench and bus functional models as required.
- Embedded CPU and subcomponent IPs with
- AXI/AHB busses and HW accelerators such as
- Cryptography, Data Compression, DMA, etc.
- Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance models
- Create abstracted FW and HW performance models
- Develop critical target code to collect IP performance key parameters
- Explore subsystem architecture performance trade-off for FW and HW optimization
- Develop and execute subsystem and block level test plans
- Develop FW/HW co-verification methodology
- Develop UVC and System Response models
- Develop and debug UVM and C-DPI test cases with integrated FW
- Improve verification metrics
- Interface with SoC integration and SoC DV teams
- Define and develop IP level DV API to support SoC level DV effort
- Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.
- Support SoC level IP emulation, silicon bring-up and debugging effort
PREFERRED EXPERIENCE:
- ASIC FW and HW design and verification experience
- Prior software development and debug experience
- Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc.)
- Knowledge about UVM methodology and C-DPI methodology
- Excellent knowledge about standard bus/interface protocols (i.e. AXI, AHB, AMBA)
- Excellent experience with firmware design on commercial microprocessors
- Excellent experience with microprocessor tool chain, compiler, assembler, debugger
- Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc.
- Strong analytical/problem solving skills and attention to details
- Being a motivated team member, and able to independently drive tasks to completion as well
- Professional interpersonal and communication skills
ACADEMIC CREDENTIALS:
- Major in Electrical or Computer Engineering.
- Master’s or PhD Degree preferred
LOCATION :
Austin, TX / Folsom , CA
#LI-SH1
#HYBRID