FPGAjobs - Jobs for Logic Designers!

RTL Design Engineer

Intel Hillsboro, Oregon

Verilog System Verilog

19h

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

19h

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

19h

yesterday

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

Principal Engineer -Technical Information

Microchip Technology Hyderabad, Telangana

FPGA RTL

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

Electrical Test Engineer III - TeraWave

Blue Origin Denver, Colorado

DFT Design for Test

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

Senior Principal Digital Engineer

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

Physical Design Power Optimization and Modeling Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

Senior Architecture Energy Modeling Engineer

NVIDIA Santa Clara, California

Verilog ASIC

Architecture Energy Modeling Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog ASIC

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

RTL Verification

Sr. Staff SoC Power & Performance Architect

Ambiq Micro, Inc. Austin, Texas

Senior Electrical Engineer I/II

Rocket Lab Pasadena, California

Verilog FPGA

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

Aug. 21, 2026

Electrical Engineering Intern (Summer 2027)

Second Order Effects Multiple Locations

VHDL Verilog

Electrical Engineering Intern (Spring 2027)

Second Order Effects Multiple Locations

VHDL Verilog

Embedded Engineer

Second Order Effects El Segundo, California

Verilog FPGA

Embedded Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

Electrical Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

Electrical Engineer

Second Order Effects El Segundo, California

Verilog FPGA

Staff Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

Senior Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

Senior STA Signoff Methodology Engineer

NVIDIA Multiple locations

ASIC STA