today

Embedded AI Tools Engineer

Analog Devices Wilmington, Massachusetts

FPGA Synthesis

17h

Staff Engineer, Digital Design Engineering

Analog Devices Multiple locations

RTL Digital Design

17h

CPU Physical Design Engineer

Intel Austin, Texas

RTL Logic Design

17h

Microarchitecture and Design Engineer - AI SoC

Intel Bangalore, India

SystemVerilog RTL

17h

Pre-Silicon SoC Validation - Technical Lead

Intel Bangalore, India

SystemVerilog RTL

17h

Pre-Si Power Performance Val & Opt Engineer (Contract)

Intel Multiple locations

FPGA RTL

17h

CPU Physical Design Engineer

Intel Austin, Texas

RTL Static Timing

17h

Senior Principal Backend Engineer (CORTEX - Autonomous SOC)

Palo Alto Networks Tel Aviv, Tel Aviv District

SOC

17h

Senior Manager-Design Engineering

Microchip Technology Multiple locations

VHDL Verilog

17h

Senior Physical Design Engineer

NVIDIA Multiple locations

STA Place and Route

17h

Senior Software Engineer, DOCA Verification

NVIDIA Multiple locations

Verification

17h

Senior Circuit Design Engineer

NVIDIA Santa Clara, California

RTL STA

17h

Senior Product Engineer, Mixed Signal SOC — TeraWave

Blue Origin Multiple locations

ASIC DFT

17h

Senior Product Engineer, Modem SOC — TeraWave

Blue Origin Central Texas

ASIC DFT

17h

Principal L1 PHY & Modem Implementation Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

FPGA ASIC

17h

ASICS Engineer-Senior to Staff

Qualcomm San Diego, California

ASIC RTL

17h

Staff Emulation Build Quality, Performance & Debug Engineer

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

17h

Emulation Performance Methodology & Debug Engineer

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

17h

Senior Emulation Performance Methodology & Debug Engineer

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

17h

Physical Design Engineer, Sr. Staff

Qualcomm Austin, Texas

ASIC RTL

17h

CPU Verification Engineer

Qualcomm Markham, Ontario

SOC Verification

17h

CPU Micro-architect/RTL Designer (Multiple Locations), Italy

Qualcomm Multiple locations

VHDL Verilog

17h

Design Verification Engineer  - Haifa

Qualcomm Haifa, Haifa District

Verilog SystemVerilog

17h

Video Design Verification - Sr Engineer

Qualcomm Bangalore, India

ASIC RTL

17h

Video Design Verification Engineer

Qualcomm Bangalore, India

ASIC RTL

17h

Senior Lead Physical Design Engineer

Qualcomm Noida, Uttar Pradesh

ASIC STA

17h

GPU Design Implementation Engineer

Qualcomm San Diego, California

ASIC RTL

17h

GPU Power Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

17h

Sr Engineer - DFT

Qualcomm Bangalore, India

FPGA ASIC

17h

RTL Design Engineer - Security /Staff

Qualcomm Bangalore, India

Verilog System Verilog

17h

Tech IP Library Characterization Engineer

Qualcomm Tijuana, Baja California

Verilog System Verilog

17h

Senior ASIC Design Engineer

HPE Juniper Networks Durham, North Carolina

Verilog System Verilog

18h

ASIC Verification/Design Engineering Intern

HPE Juniper Networks Roseville, California

Verilog ASIC

18h

Senior ASIC Physical Design Engineer

HPE Juniper Networks Ft. Collins, Colorado, United States of America; Chippewa Falls, Wisconsin, United States of America

ASIC RTL

18h

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

18h

Sr. ASIC Design Engineer

HPE Juniper Networks Roseville, California

Verilog System Verilog

18h

Senior Lead Design Engineer

NXP Semiconductors Bangalore, India

Verilog ASIC

18h

Principal Die-to-Die Interconnect Modeling Architect

Broadcom Multiple locations

Verilog RTL

18h

RTL IC Design Engineer

Broadcom Multiple locations

Verilog SystemVerilog

18h

SR, Engineer - AMS Verification

Micron Hyderabad, Telangana

Verilog SystemVerilog

18h

Verification Engineer, DMTS/SMTS/MTS

Micron Multiple locations

Verilog SystemVerilog

18h

ASIC Design Engineer, DMTS/SMTS/MTS

Micron Hyderabad, Telangana

RTL Static Timing

18h

Digital Design Engineer, DMTS/SMTS/MTS

Micron Multiple locations

Verilog SystemVerilog

18h

Design Lead (HBM/Advanced Memory Design)

Micron Richardson, Texas

Verilog SystemVerilog

18h

Staff DRAM Design Engineer

Micron Boise, Idaho

Verilog DFT

18h

Design Verification Intern

Marvell Da Nang, Đà Nẵng

Verilog SystemVerilog

18h

Physical Design Intern

Marvell Da Nang, Đà Nẵng

STA Static Timing

18h

Principal ASIC Verification Engineer

Atom Computing Austin, Texas

SystemVerilog FPGA

19h

yesterday

Sentinel - Nuclear Surety - Staff Systems Engineer - 20390

Northrop Grumman Roy, Utah

FPGA ASIC

1d

Electrical Engineer Level 4 - Digital/Mixed Signal – Dulles

Northrop Grumman Dulles, Virginia

FPGA Digital Design

1d