today

CPU Server Physical Design Engineer

Qualcomm Santa Clara, California

VHDL Verilog

35m

Low Power Design Engineer(NPU)-Sr Lead

Qualcomm Bangalore, India

RTL Synthesis

35m

yesterday

GPU Validation and Emulation Engineer, Senior

Qualcomm San Diego, California

Verilog System Verilog

23h

Modem design/RTL (Sr Staff)

Qualcomm Bangalore, India

VHDL Verilog

23h

(Structural ATPG) APAC Digital SOC Test Engineer

Qualcomm Hsinchu City, Taiwan

DFT Design for Test

23h

EDA/CAD SW Engineer (Multiple Levels)

Qualcomm San Diego, California

Verilog System Verilog

23h

FY27 Intern - Display IP Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

23h

FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

23h

Analog Engineer, Principal

Qualcomm Toronto, Ontario

VHDL Verilog

23h

FPGA Firmware Engineer / FPGA Design Engineer

Qualcomm San Diego, California

Verilog System Verilog

23h

Staff / Senior Staff Microarchitect / System Engineer

Qualcomm Noida, Uttar Pradesh

Verilog UVM

23h

Staff design Verification Engineer

Qualcomm Noida, Uttar Pradesh

Verilog System Verilog

23h

Physical Design Engineer

Qualcomm Bangalore, India

FPGA STA

23h

Staff SOC Verification Engineer

Qualcomm Noida, Uttar Pradesh

Verilog System Verilog

23h

Performance Optimization Architect/Manager

Qualcomm Bangalore, India

Verilog System Verilog

23h

Senior Lead Pre/Post Silicon Validation Engineer - SoC Security and access control Expertise

Qualcomm Bangalore, India

FPGA ASIC

23h

Senior SoC Physical Design Engineer

Qualcomm Bangalore, India

FPGA ASIC

23h

VLSI Software Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

23h

Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland

Qualcomm Cork, Munster

Verilog ASIC

23h

CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

Qualcomm Santa Clara, California

VHDL Verilog

23h

Infra Design Verification Sr Engineer

Qualcomm Bangalore, India

Verilog System Verilog

23h

Infra-Sr Staff Design Verification Engineer

Qualcomm Bangalore, India

Verilog System Verilog

23h

Test Engineer Intern - Summer 2027

NXP Semiconductors Austin, Texas

Digital Design SOC

23h

ASIC Design Automation Engineer

Broadcom USA-Colorado-Fort Collins-4380 Ziegler Road

Verilog ASIC

23h

DSP System Architect

Broadcom Irvine, California

ASIC RTL

23h

Senior Product Development Engineer

NVIDIA Santa Clara, California

ASIC Digital Design

23h

Senior DFT Engineer

NVIDIA Multiple locations

RTL DFT

23h

Power Architecture Engineer

NVIDIA Bengaluru, Karnataka

Verilog ASIC

23h

Senior Hardware Security Architect

NVIDIA Santa Clara, California

Verilog ASIC

23h

Silicon Co-design Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC Digital Design

23h

Blue Ring Mission Systems Requirements & Verification Engineer

Blue Origin Greater Seattle Area

Verification

1d

Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave

Blue Origin San Diego, California

Verilog SystemVerilog

1d

Avionics Hardware Engineer

Blue Origin Multiple locations

FPGA Design for Test

1d

Senior Electrical Engineer – TeraWave High-Speed Digital & Networking Payload Hardware

Blue Origin Greater Seattle Area

FPGA DFT

1d

Aerospace Systems Engineer III - Blue Ring Space Vehicle Requirements & Verification Architect (MTN)

Blue Origin Multiple locations

Verification

1d

Sr. Manufacturing PCBA Design & SMT Fab DFX Engineer

Blue Origin Bay Area, CA; Greater Seattle Area

FPGA ASIC

1d

Senior Manufacturing Opto-Mechanical & Sensor DFX Engineer

Blue Origin Bay Area, CA

DFT Design for Test

1d

Sr. Senior Manufacturing Surface Treatment, Sealing & Adhesion DFX Engineer

Blue Origin Bay Area, CA

DFT Design for Test

1d

Senior Electrical Engineer - Power Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

1d

Senior Electrical Engineer - Circuit Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

1d

RFIC Layout Engineer

Apple Multiple Locations

RTL SOC

1d

GPU IP Verification Engineer

Intel Bangalore, India

VHDL Verilog

1d

GPU IP Integration Model Build Engineer

Intel Bangalore, India

UVM OVM

1d

Senior PDK Support Engineer (Physical Verification)

Intel Multiple locations

SOC Verification

1d

CPU Circuit Design Engineer

Intel Bangalore, India

Verilog Digital Design

1d

Senior Engineer II - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

1d

Senior Principal FPGA Verification Engineer - $30K Sign-On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

1d

Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Multiple locations

Verilog SystemVerilog

1d

Cyber Security Operations Analyst (Tier 2 SOC)

Marvell Bangalore, India

SOC

1d

Summer Program Intern

Marvell Cordoba, Argentina

Verilog Digital Design

1d