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Principal FPGA Designer – TeraWave
Senior Engineer, Digital Design Engineering
GPU IP Lead Emulation Model Build Engineer
Design Verification Engineer
Junior CPU Verification Engineer
Digital Signal Processing Engineer
Engineering Intern (EE/CE/RF) III, Summer 2027 (Hybrid)
FPGA Engineer
Senior Power Architect, SoC Power and Thermal Management SW
Senior System Integration and Validation Engineer
ASIC Design Engineer – Clocks IP
Formal Verification Engineer
Senior System Level Testability Engineer
ASIC Design Engineer - New College Grad 2026
Senior Verification Engineer, PCIE
Principal Engineer - Layout
Senior Technical Staff Engineer - SOC Verification
Technical Safety Assessor / Architect (HW- Soc) (f/m/d)
Senior Digital Design Engineer
Principal Physical Design Engineer
Technical Director, Digital Design Methodology & Flow Architecture
NPU/AI Processor Synthesis Lead
IP Verification Lead Engineer, Sr
Senior Director, Program Management - Data Center Custom Silicon
CPU Firmware Verification and Validation
VLSI Design Engineer for Server / Data Center Products
MBIST Diagnostics Engineer, up to Sr. Staff
SOC Limits Management Architect
Emulation Performance/Debug Engineer
Physical Design Engineer, Senior Lead
Engineer- Senior
RISCV Infra System IP DV - Sr Staff Engineer
RISCV Infra System IP DV - Sr Lead Engineer
NPU AI Processor Synthesis Engineer- Sr Lead
RTL Design(Audio)-Sr Engineer
RTL Design(Audio)-Engineer
CPU Physical Design Senior Engineer
RTL Design (DDR) - Sr Lead Engineer
Senior Design Engineer(FPGA RTL)
Technical Recruiter
Technical Program Manager, Silicon/Hardware
Physical Design CPU Methodology Engineer
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