today

Engineer Digital/Principal Engineer Digital- San Diego Event

Northrop Grumman San Diego, California

VHDL FPGA

4h

Sr. Principal Digital Engineer - San Diego Event

Northrop Grumman San Diego, California

VHDL FPGA

4h

Senior Digital Design Engineer

Analog Devices Multiple locations

Verilog SystemVerilog

4h

Principal Project Manager

Analog Devices Limerick, Ireland

ASIC HDL

4h

Senior Engineer, Analog Design Engineering

Analog Devices Milan, Lombardy

Verilog SystemVerilog

4h

Staff Software Verification Engineer, Datacenter & Energy Software

Analog Devices Valencia, Valencia

Verification

4h

Senior Engineer, Design Verification Engineering

Analog Devices Shanghai, Shanghai

SystemVerilog UVM

4h

Senior Engineer, Digital Design Engineering

Analog Devices Shanghai, Shanghai

Digital Design Verification

4h

Engineer, Digital Design Engineering

Analog Devices Valencia, Valencia

Verilog SystemVerilog

4h

FVCTO - Formal Verification Engineer

Intel Bangalore, India

RTL SOC

4h

Senior FPGA Design Engineer

BAE Systems Nashua, New Hampshire

VHDL Verilog

4h

Internship: Digital Design F/M

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

4h

Senior IC Design Verification Engineer

NXP Semiconductors Kanata

Verilog System Verilog

4h

Timing & Power Analysis CAD Engineer

Marvell Bangalore, India

ASIC RTL

5h

Staff Formal Verification Engineer

SiFive Multiple locations

VHDL Verilog

5h

Front End Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

5h

Silicon, Hardware, & Photonics Engineering - Internship

Lightmatter Multiple locations

ASIC RTL

5h

Senior Post-Silicon Validation Engineer

K2 Space Seattle, Washington

FPGA ASIC

5h

Senior Post-Silicon Validation Engineer

K2 Space United States - Remote

FPGA ASIC

5h

Senior ASIC Package Design Engineer

K2 Space Seattle, Washington

ASIC SOC

5h

Senior ASIC Package Design Engineer

K2 Space United States - Remote

ASIC SOC

5h

Principal ASIC Package Design Engineer

K2 Space Seattle, Washington

ASIC SOC

5h

Principal ASIC Package Design Engineer

K2 Space United States - Remote

ASIC SOC

5h

Summer 2027 - Electrical Engineering Internship, FPGA

CesiumAstro Westminster, Colorado

VHDL Verilog

5h

DSP Designer

Fidus Systems Huntsville, Alabama

Remote FPGA ASIC

5h

Electrical Test Engineer, Intelligence Systems

Anduril Santa Ana, California

FPGA RTL

5h

yesterday

Principal / Sr. Principal PCB Layout Design Engineer

Northrop Grumman Woodland Hills, California

DFT Design for Test

1d

RTL Design Engineering Student

Intel Israel, Petah-Tikva

SystemVerilog RTL

1d

Silicon Design - Flows and Methodology Intern

Intel Guadalajara, Jalisco

Verilog System Verilog

1d

RTL Design Engineer

Intel Multiple locations

VHDL Verilog

1d

Senior DFT Logic Design Engineer

Intel Multiple locations

ASIC RTL

1d

Digital Verification Engineer - MCU

NXP Semiconductors Catania, Sicily

SystemVerilog UVM

1d

Mixed Signal Design Engineer

NXP Semiconductors Tianjin, Tianjin

SOC IP Design

1d

Architect - GPU Performance

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1d

Senior Architect, GPU and SoC Modeling

NVIDIA Santa Clara, California

SOC

1d

Senior ASIC Design Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1d

Manager, Project Management - Chip Design

NVIDIA Tel Aviv, Tel Aviv District

Verilog SystemVerilog

1d

NVTHERM SoC Verification Intern, Tegra - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

1d

Design Engineer

Silicon Labs Oslo

Digital Design Synthesis

1d

Principal Field Application Engineer

SiFive Shanghai, Shanghai

FPGA RTL

1d

Senior ASIC Diagnostic Engineer

HPE Juniper Networks Bloomington, Minnesota

ASIC

1d

Senior Principal ASIC Design Engineer

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

1d

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

1d

SoC Audio Engineer, Platform Architecture

Apple Multiple Locations

SOC IP Design

1d

Infra Systems Physical Architect

Qualcomm San Diego, California

ASIC Place and Route

1d

DRAM PHY Designer, up to Staff

Qualcomm Hsinchu City, Taiwan

ASIC RTL

1d

SMMU Senior Lead Design Verification Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1d

RTL Design (Director)

Qualcomm Hyderabad, Telangana

Digital Design Synthesis

1d

Design Verification Engineer, Senior Staff

Qualcomm Toronto, Ontario

SystemVerilog ASIC

1d

SoC Design Verification Engineer (Up to Principal Level)

Qualcomm Ho Chi Minh City, Hồ Chí Minh

SystemVerilog FPGA

1d