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Featured FPGA Engineer - Come Build Really Cool Shit with Us

MicroNova Waterford, Michigan

VHDL Verilog

20d

SoC Program Manager, Director

Qualcomm Chennai, Tamil Nadu

ASIC Synthesis

17h

Turing-Design Verification Sr Lead Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)

Qualcomm Toronto, Ontario

Verilog SystemVerilog

17h

Sr. Staff Engineer – Power Lead, Systems Architecture

Qualcomm Bangalore, India

RTL Synthesis

17h

VLSI Design & System Architect/ Engineer

Qualcomm Chennai, Tamil Nadu

VHDL Verilog

17h

NSP STA/Timing Engineer

Qualcomm Bangalore, India

FPGA ASIC

17h

CPU Design Verification Engineer (Senior level) - Cambridge, UK

Qualcomm Cambridge, England

ASIC Digital Design

17h

Physical Design Engineer

Qualcomm Markham, Ontario

ASIC RTL

17h

Power Management Systems Design and Verification Engineer

Qualcomm San Diego, California

Verification

17h

SOC Design Verification Sr Lead Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

SOC Design Verification Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

Senior Emulation Performance Methodology & Debug Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

17h

Senior SoC Physical Design Engineer

Qualcomm Bangalore, India

FPGA ASIC

17h

SoC FV/CLP Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

17h

NPU AI Processor Synthesis Engineer-Sr Lead

Qualcomm Bangalore, India

FPGA Verification

17h

Emulation Engineer - Sr/Lead/Staff Engineer

Qualcomm Hyderabad, Telangana

Verilog System Verilog

17h

Post Silicon Validation -Sr/Lead/Staff Engineer

Qualcomm Hyderabad, Telangana

Verilog System Verilog

17h

Senior Director, Project Engineering (Camera SoC) - Taiwan

Qualcomm Multiple locations

ASIC SOC

17h

“Record Searcher (Records Verification)”

CACI Remote (Any State)

Verification

17h

“Record Searcher (Records Verification)”

CACI Remote (Any State)

Verification

17h

FPGA Digital Engineer - 2

Northrop Grumman Chandler, Arizona

VHDL Verilog

17h

Principal FPGA Digital Engineer - 3

Northrop Grumman Chandler, Arizona

VHDL Verilog

17h

Senior Mixed Signal Verification Engineer

NXP Semiconductors Catania, Sicily

SystemVerilog Digital Design

17h

ASIC Package Design Project Manager

Broadcom Fort Collins, Colorado

ASIC

17h

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

Staff Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog RTL

17h

SoC Power and Performance Engineer

Intel Santa Clara, California

SOC

17h

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

18h

ASIC Principal Engineer

HPE Juniper Networks Bengaluru, Karnataka

Verilog ASIC

18h

VLSI Engineer II Graduate

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

18h

Systems / Software Engineer I Graduate

HPE Juniper Networks Roseville, California

FPGA Logic Design

18h

VLSI Engineer I Graduate

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

18h

Digital IC Design Intern, BS - Summer 2027

Marvell Multiple locations

Verilog ASIC

18h

Digital IC Design Intern, MS - Summer 2027

Marvell Multiple locations

Verilog ASIC

18h

CPU Memory Subsystem Verification Engineer

Apple Multiple Locations

Verification

18h

GPU RTL Design Engineer

Apple San Diego, California

18h

HLS Software Systems Engineer ll - Lunar Permanence

Blue Origin Denver, Colorado

Verification

18h

HLS Autonomy Software Systems Engineer III

Blue Origin Denver, Colorado

HLS Verification

18h

Sr HLS Software Verification Engineer – Lunar Permanence

Blue Origin Denver, Colorado

Verification

18h

Engineer II - Digital Design

Microchip Technology Colorado Springs, Colorado

Logic Design Synthesis

18h

ASIC Verification Engineer - Clocks

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

18h

Senior GPU Memory Architect

NVIDIA Multiple locations

VHDL Verilog

18h

Associate Staff Design Modeling Egineer

Silicon Labs Austin, Texas

RTL UVM

18h