today

Principal Engineer - Verification

Microchip Technology Chennai, Tamil Nadu

17h

Senior Technical Staff Engineer - Analog & Mixed Signal Design

Microchip Technology Bangalore, India

Verilog SystemVerilog

17h

Senior Manager- SOC Verification

Microchip Technology Chandler, Arizona

SystemVerilog RTL

17h

Technical Staff Engineer - Verification

Microchip Technology Hyderabad, Telangana

VHDL Verilog

17h

PCB Layout Design Engineer

Northrop Grumman Woodland Hills, California

DFT Design for Test

17h

Principal Electrical Engineer (FPGA Design Engineer)

Northrop Grumman San Diego, California

FPGA UVM

17h

Electrical Engineer – Integrated Analog/Digital Design Level 3 /4

Northrop Grumman Sunnyvale, California

FPGA Digital Design

17h

Digital ASIC Design Engineer

Draper Cambridge, Massachusetts

VHDL Verilog

17h

Physical Design Engineer

Qualcomm Santa Clara, California

ASIC RTL

17h

Senior Hardware Engineer - SoC Architecture & Design - Qualcomm - Grenoble, France

Qualcomm Grenoble, Auvergne-Rhône-Alpes

ASIC RTL

17h

SOC Design Verification Sr Engineer

Qualcomm Bangalore, India

ASIC RTL

17h

NPI Program Manager (Staff)

Qualcomm Santa Clara, California

ASIC DFT

17h

Peripherals (Ethernet) Validation Engineer – Senior Engineer

Qualcomm Bangalore, India

ASIC SOC

17h

CPU Firmware Verification and Validation Engineer

Qualcomm Bangalore, India

17h

Senior Staff Engineer - Microcontroller Sub-System Design

Qualcomm Cork, Munster

ASIC RTL

17h

NPU Design Verification Sr Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

17h

DSP / NPU Design Verification Sr Staff Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

17h

RTL Design Engineer -Sr Lead

Qualcomm Bangalore, India

Verilog SystemVerilog

17h

RTL(IPA Design/WRD) - Sr Lead

Qualcomm Bangalore, India

VHDL Verilog

17h

Wireless RTL Design Engineer

Apple Multiple Locations

RTL Logic Design

18h

Staff Design Reliability Verification Engineer

Micron Boise, Idaho

Verification

18h

SENIOR ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

18h

Staff Engineer, RTL Design

Micron Hyderabad, Telangana

Verilog RTL

18h

Principal Compute Pathfinding ASIC Design

Micron Multiple locations

Verilog SystemVerilog

18h

VLSI Engineer I - 0T1191

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

18h

Design Verification Manager

Semtech Multiple locations

VHDL Verilog

18h

Sr. Mixed Signal/RF Test Engineer

NXP Semiconductors Irvine, California

DFT Design for Test

18h

Principal RFIC-PLL Design Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog Digital Design

18h

Senior Analog Mixed-Signal Design Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog SystemVerilog

18h

Principal Analog Mixed-Signal IC Design Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog Digital Design

18h

Principal Analog Mixed-Signal Design Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog SystemVerilog

18h

Senior FPGA/Prototype Design Engineer 

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog System Verilog

18h

Senior FPGA/Prototype Design Engineer 

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog System Verilog

18h

Principal FPGA/Prototype Design engineer 

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog System Verilog

18h

Principal FPGA/Prototype Design engineer 

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog System Verilog

18h

Chassis IP Design Engineer

Intel Bangalore, India

Verilog System Verilog

18h

Chassis IP Senior Design Engineer

Intel Bangalore, India

Verilog System Verilog

18h

GPU Logic Design Engineer

Intel Bangalore, India

RTL Register Transfer

18h

GPU Senior Logic Design Engineer

Intel Bangalore, India

Verilog System Verilog

18h

E-core CPU Clock Design Engineer

Intel Penang, Malaysia

Synthesis SOC

18h

CPU Validation Engineer

Intel Austin, Texas

Verilog System Verilog

18h

SOC Emulation Validation Engineer

Intel Multiple locations

VHDL Verilog

18h

SoC Functional Validation Engineer - Memory Pre-silicon Validation

Intel Penang, Malaysia

FPGA SOC

18h

SoC Functional Validation Engineer – Central Execution Platform Enabling

Intel Penang, Malaysia

SOC

18h

SoC Functional Validation Engineer – Central Execution Platform Enabling

Intel Penang, Malaysia

SOC

18h

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Broadcom Multiple locations

Verilog System Verilog

18h

Senior Engineer, Logic Equivalence CAD

Marvell Bangalore, India

RTL Synthesis

18h

Senior Staff Engineer - Emulation

Marvell Bangalore, India

FPGA RTL

18h

Principal Engineer, Emulation

Marvell Bangalore, India

FPGA RTL

18h

Senior Principal Engineer, Emulation

Marvell Bangalore, India

FPGA RTL

18h