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Senior SoC Design Engineer
Senior Staff Design Engineer
RFIC Digital Verification Sr Engineer
GPU DV Staff/Senior Staff Engineer
System FPGA Engineer
Network Processor IP Verification Sr Lead Engineer
Physical Design Engineer, Sr Staff
CPU Physical Electrical Analysis Engineer, Santa Clara/Austin
CPU Physical Design Timing Engineer
RFIC Design Engineer
Director, Yield Architecture & Engineering
SOC Power Design Engineer
Serdes PHY Analog Design Engineer
Software Engineer, Senior
Firmware Engineer – SerDes PHY (all levels)
Silicon Validation Engineer, Electrical and Optical Systems - (all levels)
Digital Design Verification Engineer, Staff
Memory Designer
CAD RTL/DV Infrastructure Engineer, Staff
AI/ML Camera Lead Engineer
GPU Design Verification Engineer, Staff
NoC (RTL) Design-Sr Lead/Staff/Sr Staff
GPU Compiler Engineer - Cambridge, UK
Senior Staff Formal Verification Engineer
Graphics ASICS Hardware Design Engineer
System Performance Modeling Engineer
Pre-Silicon verification engineer
CPU Verification Student
Functional Safety Intern - Spring 2027
Entry Level Digital Verification Engineer
Entry Level Digital Design Engineer
Entry Level DFT Design Engineer
Entry Level Digital Design Engineer
Digital Verification Intern - Summer 2027
Digital Design Intern - Summer 2027
SOC DFT Intern - Summer 2027
Digital Design Intern - Spring 2027
SOC DFT Intern - Spring 2027
Digital Design Intern - Spring 2027
Test Engineer (NPI Development)
AI/ML ASIC Design and Implementation Automation Intern - Summer 2027
Lead PPA Engineer
Emulation Engineer
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