today

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

8h

VLSI Integration Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

8h

Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

Verilog System Verilog

8h

Senior Software Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

8h

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

8h

Physical Design STA CAD Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Static Timing

8h

Director of Physical Design

Ambiq Micro, Inc. Austin, Texas

RTL Synthesis

8h

Principal Physical Verification Engineer

Celero Communications, Inc. San Jose, California

Verification

8h

Principal Physical Design Engineer

Celero Communications, Inc. San Jose, California

ASIC RTL

8h

Principal Analog Mixed Signal ASIC Layout Engineer

Draper Cambridge, Massachusetts

ASIC Verification

8h

Microelectronics Integration and Test Engineer

Draper Cambridge, Massachusetts

ASIC Design for Test

8h

Mixed Signal Design Verification Engineer

Intel Bangalore, India

Verilog System Verilog

8h

Graduate FPGA Engineer (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

8h

FPGA Internship (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

8h

Senior NVM Digital Designer

Mythic AI Palo Alto, California

Verilog SystemVerilog

8h

Senior Mixed Signal / Memory Circuit Designer

Mythic AI Palo Alto, California

Verilog System Verilog

8h

Software Engineer - FPGA-Accelerated RTL Simulation

SiFive Berkeley, California

FPGA ASIC

8h

Digital Verification Engineer - MCU

NXP Semiconductors Catania, Sicily

SystemVerilog UVM

8h

yesterday

Senior Staff RTL Design /Verification

Marvell IL - Petah Tikva; Yokneam

SystemVerilog RTL

14h

DFT Principal Engineer

Marvell Petah-Tikva; Yokneam

Verilog SystemVerilog

14h

Design Verification, Manager

Marvell Ho Chi Minh City, Hồ Chí Minh

SystemVerilog UVM

14h

Design Verification Senior Staff Engineer

Marvell IL - Petah Tikva

Verilog SystemVerilog

14h

Senior Manager, ASIC Design

Marvell Santa Clara, California

Verilog SystemVerilog

14h

Staff to Senior Staff Engineer, DFT

Marvell Bangalore, India

RTL STA

14h

DSP Firmware Engineer

Marvell Cordoba, Argentina

Verilog SystemVerilog

14h

Principal Engineer, Verification

Marvell Santa Clara, California

Verilog System Verilog

14h

Principal Engineer - Digital IC Design

Marvell Bangalore, India

Verilog ASIC

14h

Principal Design Verification Engineer

Marvell Bangalore, India

Verilog System Verilog

14h

Senior Principal Engineer, Design Verification

Marvell Ottawa, Ontario

Verilog System Verilog

14h

DFT Manager

Marvell Ottawa, Ontario

ASIC RTL

14h

Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon

Marvell Santa Clara, California

RTL SOC

14h

Hardware & Silicon Validation Senior Staff Engineer

Marvell Santa Clara, California

ASIC Digital Design

14h

Principal Test Engineer (Optical Module)

Marvell Santa Clara, California

ASIC DFT

14h

Analog Design - Senior Principal Engineer

Marvell Bangalore, India

RTL DFT

14h

Senior Staff Digital Design Engineer

Marvell Ottawa, Ontario

Verilog System Verilog

14h

Design/DSP/Verification Intern - PhD Degree

Marvell Santa Clara, California

SOC

14h

Principal Verification Engineer

Marvell Santa Clara, California

Verilog System Verilog

14h

Principal AMS verification engineer

Marvell Bangalore, India

Verilog Verification

14h

Physical Design Intern

Marvell Cordoba, Argentina

ASIC Static Timing

14h

Senior / Staff Verification Engineer - RF/TIA (Analog Mixed Signal)

Marvell Singapore, Central Singapore

Verilog Verification

14h

Design Verification Engineer - Early Career

Marvell Multiple locations

VHDL Verilog

14h

Principal Engineer - PCIe RTL Design

Marvell Bangalore, India

Verilog SystemVerilog

14h

Design Verification Engineer

Marvell IL - Petah Tikva; Yokneam

Verilog System Verilog

14h

Senior Principal Memory Architect

Marvell Multiple locations

ASIC RTL

14h

Senior Staff Verification Engineer

Marvell Pune, Maharashtra

SystemVerilog UVM

14h

Digital IC Design Senior Staff Engineer

Marvell Petah-Tikva

Verilog SystemVerilog

14h

Senior Design Engineer

Marvell Petah-Tikva

Verilog SystemVerilog

14h

Design Verification Senior Staff Engineer

Marvell Petah-Tikva

SystemVerilog ASIC

14h

Principle Verification Engineer

Marvell IL - Petah Tikva

SystemVerilog ASIC

14h

Technical Lead IC Design/Principal - Micro-architecture, RTL Design

Marvell Ottawa, Ontario

Verilog System Verilog

14h