today

Principal SoC DFT Engineer, HBM

Micron Multiple locations

ASIC RTL

17h

SENIOR ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

17h

VLSI Design Verification Masters Level Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

VHDL Verilog

17h

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

Senior SoC Debug Engineer

Qualcomm San Diego, California

ASIC RTL

17h

Senior Systems Design Engineer - Qualcomm - Sophia or Guyancourt - France

Qualcomm Guyancourt, Île-de-France

Verilog SystemVerilog

17h

Senior Systems Verification Engineer - Qualcomm - Sophia or Guyancourt, France

Qualcomm Guyancourt, Île-de-France

Verilog FPGA

17h

Design Engineer, Senior Staff/Manager

Qualcomm Noida, Uttar Pradesh

ASIC RTL

17h

CPU Design Sr Staff Verification Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

CPU Server Physical Design Engineer

Qualcomm Santa Clara, California

VHDL Verilog

17h

Principal CPU PPA Pathfinding Engineer

Qualcomm San Diego, California

ASIC RTL

17h

NOC Design Verification Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

17h

NOC DV Sr Lead Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

SOC Design Engineer

Qualcomm Multiple locations

VHDL Verilog

17h

RTL Design(Camera) - Sr Engineer

Qualcomm Bangalore, India

Logic Design Verification

17h

Silicon Test Engineer, Senior

Qualcomm Tijuana, Baja California

Digital Design DFT

17h

SOC Power Design -Staff/Sr Staff

Qualcomm Bangalore, India

FPGA Verification

17h

Senior Emulation Engineer

Axiado Hyderabad, Telangana

SystemVerilog RTL

17h

Staff Engineer, Firmware Engineering

Analog Devices Multiple locations

Verilog SystemVerilog

17h

Senior Engineer, Digital Verification

Analog Devices Multiple locations

SystemVerilog UVM

17h

ASIC Verification Engineer

NVIDIA Hyderabad, Telangana

Verilog System Verilog

18h

ASIC Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

18h

ASIC Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

18h

Senior SoC Software Engineer

NVIDIA Santa Clara, California

SOC

18h

Senior Verification Engineer, Switch SoC

NVIDIA Bengaluru, Karnataka

Verilog UVM

18h

Senior Chip Design Verification Engineer

NVIDIA Multiple locations

ASIC RTL

18h

Formal Verification Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog System Verilog

18h

Principal Hardware Security Architect, Advanced Technologies and Threat Modeling

NVIDIA Santa Clara, California

Verilog ASIC

18h

SoC Software Engineer – New College Graduate 2026

NVIDIA Santa Clara, California

ASIC SOC

18h

SoC Software Engineer - New College Grad 2027

NVIDIA Santa Clara, California

ASIC SOC

18h

Senior ASIC Design Engineer - Memory Subsystem

NVIDIA Santa Clara, California

VHDL Verilog

18h

Low Power ASIC Engineer - New College Grad 2027

NVIDIA Santa Clara, California

Verilog SystemVerilog

18h

ASIC Verification Engineer - New College Grad 2027

NVIDIA Santa Clara, California

VHDL Verilog

18h

Data Center SoC Power Architect

Intel Santa Clara, California

SOC

18h

Senior GPU Physical Design Engineer

Intel Multiple locations

ASIC RTL

18h

Senior Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

18h

Principal Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

18h

HLS Software Systems Engineer III

Blue Origin Multiple locations

HLS Verification

18h

Analog Mixed-Signal IC Design Engineer (Data Converters) - TeraWave

Blue Origin Multiple locations

SystemVerilog Digital Design

18h

Static Timing Analysis Design Engineer / Physical Design

NXP Semiconductors Austin, Texas

ASIC STA

18h

Sr RF/Mixed Signal Test Engineer

NXP Semiconductors Irvine, California

DFT Design for Test

18h

Static Timing Analysis Design Engineer / Physical Design

NXP Semiconductors Austin, Texas

ASIC STA

18h

Physical Design Intern - Master's Degree

Marvell Singapore, Central Singapore

ASIC RTL

18h

Design Verification- Intern

Marvell Petah-Tikva

Verilog System Verilog

18h

Principal Validation Lead

Marvell Santa Clara, California

ASIC DFT

18h

Sr. Staff Validation Engineer

Marvell Santa Clara, California

ASIC DFT

18h

Principal Software Engineer

BAE Systems Nashua, New Hampshire

VHDL Verilog

18h

Senior Systems Engineer – Aftermarket & Production Support

BAE Systems Endicott, New York, United States

VHDL FPGA

18h