today

Senior System Software Engineer, SOC

NVIDIA Multiple locations

SOC

4h

Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel Multiple locations

Verification

4h

Senior CPU Logic Design Engineer

Intel Haifa, Haifa District

SystemVerilog RTL

4h

CPU Pre-Silicon Verification Lead

Intel Bangalore, India

Verilog System Verilog

4h

Senior CPU RTL Design Engineer

Intel Multiple locations

Verilog System Verilog

4h

Design Eng 3

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

4h

FE Engineering

Apple Cupertino, California

Verilog SystemVerilog

4h

Design Verification Engineer

Apple Cupertino, California

Verilog System Verilog

4h

FE Engineer

Apple Cupertino, California

Verilog System Verilog

4h

Design Verification

Apple Cupertino, California

Verilog SystemVerilog

4h

Design Verification Engineer

Apple Cupertino, California

Verilog SystemVerilog

4h

Senior Manager – Characterization

Microchip Technology Hyderabad, Telangana

VHDL Verilog

4h

Engineer II - Design

Microchip Technology Hauppauge, New York

VHDL Verilog

4h

CPU Design Verification - Principal Engineer

Qualcomm Bangalore, India

Verilog System Verilog

5h

RTL (NOC)Design -Sr Lead/Staff

Qualcomm Noida, Uttar Pradesh

ASIC RTL

5h

SoC Design & Synthesis Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

5h

RTL(NOC)Design-Sr Lead/Staff

Qualcomm Bangalore, India

FPGA Verification

5h

Staff SoC Architect, AI Data Center

Qualcomm San Diego, California

SOC

5h

Senior ASIC Verification Engineer, Low Power AI Subsystems

Qualcomm Markham, Ontario

VHDL Verilog

5h

NPU Physical Design Engineer Sr Staff

Qualcomm Bangalore, India

FPGA STA

5h

Program Manager

Qualcomm Taipei, Taipei

ASIC Digital Design

5h

Distinguished Technologist, VLSI Engineering

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

5h

Design Verification Intern

Marvell Petah-Tikva; IL - Yokneam

SOC Verification

5h

Design For Test Intern, MS - Summer 2027

Marvell Santa Clara, California

Verilog System Verilog

5h

SRAM Circuit Design Intern, MS - Summer 2027

Marvell Burlington, Vermont

VHDL Verilog

5h

Senior Staff Digital Design Engineer

Marvell Multiple locations

SystemVerilog FPGA

5h

Sr MSIAM SOC Engineer (Unit 42)

Palo Alto Networks Tel Aviv, Tel Aviv District

SOC

5h

Senior FPGA Engineer

AeroVironment Sunrise, Florida

VHDL FPGA

5h

FPGA Engineer

AeroVironment Albuquerque, New Mexico

VHDL Verilog

5h

FPGA Engineer

AeroVironment Albuquerque, New Mexico

VHDL Verilog

5h

Senior principal DFT engineer

NXP Semiconductors Bangalore, India

Digital Design Verification

5h

Principal Digital Engineer or Sr. Principal Digital Engineer

Northrop Grumman Baltimore, Maryland

VHDL FPGA

5h

Staff Systems Signal Processing Engineer

Northrop Grumman Baltimore, Maryland

VHDL Verilog

5h

FPGA Digital Design Engineer Level 4 (AHT)

Northrop Grumman Northridge, California

VHDL Verilog

5h

Embedded Software Verification Engineer – Surgical Robotics (Cambridge, MA)

Philips Cambridge, England

Verification

5h

RF Applications Engineer

Analog Devices Limerick, Ireland

FPGA SOC

5h

Senior Staff AI Accelerator Performance Architect

Cerebras Systems Sunnyvale, California

FPGA RTL

6h

Lead Electrical Test Engineer, Customer Hardware (Starlink)

SpaceX Bastrop, Texas

DFT Design for Test

6h

yesterday

Staff Engineer Formal(IOMMU-N)

SiFive Bengaluru, Karnataka

FPGA ASIC

1d

Senior Engineer II - Physical Design

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1d

Staff Per Diem-FPGA Electronics

Draper Cambridge, Massachusetts

1d

Senior Lead Verification Engineer, Digital IP

NXP Semiconductors Bangalore, India

Verilog System Verilog

1d

Stage ingénieur : Analyse de la consommation et optimisation des tests pour les System-on-Chip (SoC) de nouvelle génération (H/F)

NXP Semiconductors Sophia-Antipolis (Valbonne)

Digital Design DFT

1d

Stage Ingénieur : Vérification de Performance et Modélisation de Systèmes sur Puce (SoC) (H/F)

NXP Semiconductors Grenoble, Auvergne-Rhône-Alpes

SOC Verification

1d

Stage Ingénieur : Application de l'Intelligence Artificielle à l'intégration de blocs RTL (ASIC/FPGA) (H/F)

NXP Semiconductors Sophia-Antipolis (Valbonne)

VHDL Verilog

1d

Stage Ingénieur : Développement d’un outil d’analyse de performance pour simulations hardware (H/F)

NXP Semiconductors Caen, Normandie

VHDL Verilog

1d

Stage ingénieur: Amélioration de la vérification d’un contrôleur I2C avec UVM, preuve formelle et IA (H/F)

NXP Semiconductors Caen, Normandie

Verilog SystemVerilog

1d

Stage Ingénieur : Évaluation des Outils de Vérification des Transitions de Domaines d'Horloge (CDC) assistés par IA (H/F)

NXP Semiconductors Grenoble, Auvergne-Rhône-Alpes

RTL Synthesis

1d

DFT Engineer

NXP Semiconductors Tianjin, Tianjin

VHDL Verilog

1d

Senior Methodologist for AIML Enhanced Design/Verification

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1d