today

Sentinel - Nuclear Surety - Staff Systems Engineer - 20390

Northrop Grumman Roy, Utah

FPGA ASIC

17h

Electrical Engineer Level 4 - Digital/Mixed Signal – Dulles

Northrop Grumman Dulles, Virginia

FPGA Digital Design

17h

2027 Associate Digital Signal Processing Engineer - Cincinnati OH

Northrop Grumman Cincinnati, Ohio

VHDL FPGA

17h

Engineer Digital - Level 5 - Linthicum

Northrop Grumman Linthicum, Maryland

FPGA Digital Design

17h

Staff Engineer Electrical

Northrop Grumman Gilbert, Arizona

FPGA Digital Design

17h

Senior Engineer, Digital Verification

Analog Devices Multiple locations

Verilog SystemVerilog

17h

Staff Digital Design Engineer

Analog Devices Multiple locations

SystemVerilog ASIC

17h

Director, Analog Design

Analog Devices Multiple locations

Digital Design Design for Test

17h

SoC Functional Validation Engineer – Core (CRE) Domain

Intel Penang, Malaysia

SOC

17h

E-Core CPU Design Automation Engineer

Intel Penang, Malaysia

Logic Design Static Timing

17h

SoC Functional Validation Engineer - Functional Safety

Intel Penang, Malaysia

SOC

17h

E-Core (Atom) CPU Layout Design Engineer

Intel Multiple locations

Digital Design SOC

17h

SoC Chip Lead

Lattice Semiconductor San Jose, California

SystemVerilog FPGA

17h

Senior Firmware Engineer

Lattice Semiconductor Duluth, Georgia

FPGA SOC

17h

Product Engineer

Lattice Semiconductor Manila, Metro Manila

VHDL Verilog

17h

DV CAD Engineer

Qualcomm California Non-Bay Area - Remote, United States of America

RTL Digital Design

17h

SOC Design Verification Engineer

Qualcomm San Diego, California

ASIC RTL

17h

Director , Engineering (GPU Physical Design)

Qualcomm Bangalore, India

ASIC STA

17h

Memory Designer

Qualcomm San Diego, California

ASIC RTL

17h

RISC-V System IP Sr Design Engineer

Qualcomm Chennai, Tamil Nadu

Verilog RTL

17h

RISC-V System IP Design Lead

Qualcomm Chennai, Tamil Nadu

Verilog RTL

17h

Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

17h

Next Gen, High-Speed, Memory and Cache Controller Design Engineer

Qualcomm San Diego, California

ASIC RTL

17h

DDRSS Systems Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

17h

EDA/CAD Software Engineer, Staff

Qualcomm San Diego, California

Verilog System Verilog

17h

FPGA Design & Firmware Engineer, Staff

Qualcomm San Diego, California

Verilog SystemVerilog

17h

FPGA Design & Firmware Engineer, Staff

Qualcomm San Diego, California

Verilog SystemVerilog

17h

Memory Circuit Design Engineer

Qualcomm Bangalore, India

ASIC SOC

17h

CPU Core Validation Engineer (Staff/Senior Staff) - CPU Pipeline and uarch experts

Qualcomm Bangalore, India

FPGA SOC

17h

Design Engineer - Hod Hasharon

Qualcomm Hod HaSharon, Central District

ASIC SOC

17h

Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

17h

CPU Post-Silicon Performance Engineer

Qualcomm Santa Clara, California

FPGA SOC

17h

Mask Layout Designer

Qualcomm Tijuana, Baja California

Digital Design IP Design

17h

Technical Staff Engineer - Verification

Microchip Technology Hyderabad, Telangana

SystemVerilog ASIC

17h

Technical Staff Engineer – Design & Product Validation

Microchip Technology Burnaby, British Columbia

VHDL SystemVerilog

17h

ASIC Design Engineer Intern

HPE Juniper Networks Sunnyvale, California

ASIC RTL

17h

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

17h

Senior Principal Systems Engineer - Radar

BAE Systems Huntsville, Alabama

VHDL FPGA

18h

SoC Verification

NXP Semiconductors Multiple locations

VHDL Verilog

18h

Senior Physical Design AI Engineer

NVIDIA Bengaluru, Karnataka

RTL Place and Route

18h

Senior Physical Verification Engineer

NVIDIA Bengaluru, Karnataka

Synthesis SOC

18h

Senior VLSI Methodology Engineer

NVIDIA Santa Clara, California

Place and Route Synthesis

18h

Senior Full-Chip RTL Integration Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

18h

Senior SoC Software Engineer

NVIDIA Santa Clara, California

SOC

18h

Senior Director, ATE Test Development

NVIDIA Santa Clara, California

ASIC DFT

18h

Principal GPU Memory Architect

NVIDIA Santa Clara, California

VHDL Verilog

18h

Senior Design Verification Engineer - GPU Memory Subsystem

NVIDIA Durham, North Carolina

Verilog System Verilog

18h

Principal Field Application Engineer

SiFive Shanghai, Shanghai

FPGA RTL

18h

Apply Now! India Campus Team

Micron Multiple locations

ASIC SOC

18h

Principal Engineer, HIG-HBM Design

Micron Richardson, Texas

ASIC RTL

18h