today

Sr. Principal Digital Engineer

Northrop Grumman Multiple locations

VHDL FPGA

17h

Engineer II - Electrical

BAE Systems Dallas, Texas

VHDL Verilog

17h

Principal Engineer, Analog Design Engineering

Analog Devices Multiple locations

Verilog SOC

17h

Digital Design Engineer, DFT

Analog Devices Philippines, Bonifacio Global City

ASIC DFT

17h

Senior Formal Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

17h

PMU ASIC Engineer - New College Graduate 2027

NVIDIA Shanghai, Shanghai

ASIC RTL

17h

PMU Verification Engineer - New College Graduate, 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

17h

ASIC Verification Engineer - Hardware

NVIDIA Shanghai, Shanghai

SystemVerilog ASIC

17h

Senior DFX Engineer

NVIDIA Shanghai, Shanghai

Verilog ASIC

17h

DFX Engineering

NVIDIA Shanghai, Shanghai

Verilog ASIC

17h

System Software Engineering Intern, GPU and SOC - Summer 2027

NVIDIA Taipei, Taipei

SOC

17h

Formal Verification Engineer - New College Graduate

NVIDIA Budapest, Budapest

Verilog System Verilog

17h

Software Verification Engineer, DOCA

NVIDIA Multiple locations

Verification

17h

DFT Intern - 2027

NVIDIA Shanghai, Shanghai

Verilog Logic Design

17h

VLSI Logic Design Intern

HPE Juniper Networks Chippewa Falls, Wisconsin, United States of America

Verilog System Verilog

18h

ASIC Verification Engineering Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

18h

VLSI Design Verification Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

VHDL Verilog

18h

VLSI Logic Design Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

Verilog System Verilog

18h

ASIC Intern

HPE Juniper Networks Sunnyvale, California

VHDL Verilog

18h

Physical Design Engineering Student

Intel Haifa, Haifa District

Digital Design Place and Route

18h

SoC Design Verification Engineer

Intel Bangalore, India

RTL UVM

18h

SoC Design Verification Engineer

Intel Bangalore, India

RTL UVM

18h

SoC Design Verification Engineer

Intel Bangalore, India

RTL UVM

18h

Logic Design / Design Verification Engineering Undergraduate Intern

Intel Leixlip, Leinster

VHDL Verilog

18h

Ethernet System Integration Engineer

Intel Hillsboro, Oregon

ASIC SOC

18h

Ethernet System Integration Engineer

Intel Hillsboro, Oregon

ASIC SOC

18h

Project Engineer II – FPGA Lead & Design Engineer

BAE Systems Westminster, Colorado

VHDL Verilog

18h

Senior Principal Engineer

NXP Semiconductors Noida, Uttar Pradesh

Digital Design Synthesis

18h

Technical Lead Verification

NXP Semiconductors Bangalore, India

Verification

18h

Recruiter (Fixed Term)

Blue Origin Greater Seattle Area

ASIC RTL

18h

ASIC Design Engineer – Fabric/Interconnect

Apple Multiple Locations

RTL STA

18h

Senior Engineer IP Verification - Digital Design Verification

Micron Hyderabad, Telangana

RTL UVM

18h

Staff Engineer IP Verification - Digital Design Verification

Micron Hyderabad, Telangana

RTL UVM

18h

ENGINEER, DESIGN

Micron Avezzano, Abruzzo

ASIC RTL

18h

SR ENGINEER, DESIGN

Micron Avezzano, Abruzzo

RTL Logic Design

18h

SR ENGINEER, DESIGN

Micron Avezzano, Abruzzo

ASIC RTL

18h

ENGINEER, DESIGN

Micron Avezzano, Abruzzo

FPGA RTL

18h

Senior System Level Verification Engineer

Axiado Hyderabad, Telangana

FPGA ASIC

18h

Senior System Level Verification Engineer

Axiado San Jose, California

FPGA ASIC

18h

Senior Customer Support Engineer, Physical Design

SiFive Bengaluru, Karnataka

RTL Place and Route

18h

ASIC Modelling Engineer, Senior - Cork, Ireland

Qualcomm Cork, Munster

ASIC RTL

18h

Near-Memory Compute System Validation Engineer

Qualcomm San Diego, California

FPGA ASIC

18h

NOC DV Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

18h

NOC DV Sr Engineer

Qualcomm Bangalore, India

Verilog System Verilog

18h

CPU STA Engineer, Sr Engineer

Qualcomm Hyderabad, Telangana

Verilog FPGA

18h

NPU Design Verification Sr Lead Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

18h

NPU Staff Design Verification Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

18h

ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr

Qualcomm Bangalore, India

Verilog ASIC

18h

Staff Design Engineer - Cork, Ireland

Qualcomm Cork, Munster

ASIC RTL

18h

ASIC Design Verification Engineer

Broadcom Multiple locations

ASIC RTL

19h