today

Senior Hardware Design Engineer

Intel Israel, Petah-Tikva

Verilog FPGA

17h

CPU Core Physical Design Technical Graduate Intern, Spring

Intel Folsom, California

ASIC STA

17h

AI Compiler Formal Verification Intern

NVIDIA Multiple locations

Verification

17h

Tools and Methodology Engineer, CAD DFT (RDSS Intern)

NVIDIA Multiple locations

Verilog DFT

17h

Software Engineer – DFT CAD Tools (RDSS Intern)

NVIDIA Taipei, Taipei

Verilog ASIC

17h

ASIC Physical Design Engineer

NVIDIA Shanghai, Shanghai

ASIC RTL

17h

Senior ASIC Design Engineer

NVIDIA Multiple locations

Verilog ASIC

17h

Senior ASIC Timing Engineer

NVIDIA Multiple locations

ASIC RTL

17h

NVIDIA 2027 Ignite Internships: Hardware Engineering

NVIDIA Santa Clara, California

VHDL Verilog

17h

Hardware Engineer Intern, BS - Summer 2027

Marvell Santa Clara, California

FPGA RTL

17h

Physical Design Engineer

Broadcom Pune, Maharashtra

Digital Design STA

17h

Camera Frontend Implementation Engineer

Qualcomm Vancouver, British Columbia

ASIC RTL

17h

SOC Design Verification Staff Engineer

Qualcomm Bangalore, India

ASIC RTL

17h

High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform)

Qualcomm San Diego, California

FPGA ASIC

17h

System Validation Lead (Premium Mobile Platforms)

Qualcomm San Diego, California

FPGA ASIC

17h

ASICS Design Verification Engineer (Vancouver OR Markham)

Qualcomm Multiple locations

VHDL Verilog

17h

RISCV Infra System IP Design-Sr / Lead / Staff Engineer

Qualcomm Chennai, Tamil Nadu

Verilog RTL

17h

CPU RAS and Manageability Controller Firmware Developer, Staff

Qualcomm Bangalore, India

FPGA SOC

17h

Design Verification - Senior Staff Engineer/Mgr

Qualcomm Hyderabad, Telangana

ASIC SOC

17h

Digital Design Engineer, DFT

Analog Devices Dallas, Texas

ASIC DFT

17h

Senior ASIC Emulation Engineer

Palo Alto Networks Headquarters, California

Verilog SystemVerilog

17h

SR, Engineer - AMS Verification

Micron Hyderabad, Telangana

Verilog SystemVerilog

17h

Staff Engineer, ASIC Gen AI

Micron Multiple locations

ASIC

17h

Intern - Next-Generation HBM Architecture

Micron Folsom, California

SystemVerilog RTL

17h

Director, Custom HBM Design and Architecture

Micron Multiple locations

SystemVerilog RTL

17h

Electrical Engineering Systems Architect - 6

Northrop Grumman Chandler, Arizona

FPGA SOC

18h

Safety Engineer

NXP Semiconductors Multiple locations

DFT SOC

18h

PRINCIPAL PHYSICAL VERIFICATION ENGINEER

NXP Semiconductors Bangalore, India

SOC Verification

18h

Staff SoC Verification Engineer

NXP Semiconductors Bangalore, India

Verilog System Verilog

18h

Stage Ingénieur : Automatisation de la génération et de la maintenance de modèles AMS à l’aide de l’IA (F/H)

NXP Semiconductors Toulouse, Occitanie

Verilog SystemVerilog

18h

Stage Ingénieur : Vérification d’architectures d’interconnexion pour SoC automobiles (F/H)

NXP Semiconductors Toulouse, Occitanie

SystemVerilog RTL

18h

Stage Ingénieur : Conception Numérique IP et Circuit Intégrés (F/H)

NXP Semiconductors Toulouse, Occitanie

VHDL Verilog

18h

Senior SOC Design For Test Engineer

NXP Semiconductors Grenoble, Auvergne-Rhône-Alpes

Verilog SystemVerilog

18h

MCU Power Architect

NXP Semiconductors Catania, Sicily

Digital Design DFT

18h

Junior Analog Design Engineer

NXP Semiconductors Catania, Sicily

Digital Design DFT

18h

FPGA Design Lead - Digital Signal Processing (DSP)

BAE Systems Multiple locations

VHDL Verilog

18h

Technical Staff Engineer-Design

Microchip Technology Bangalore, India

Verilog System Verilog

18h

Senior Engineer I - Validation (ASIC)

Microchip Technology Burnaby, British Columbia

ASIC

18h

Principal Engineer - Verification

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

18h

PCB Design Librarian III

Blue Origin Multiple locations

FPGA ASIC

18h

Senior Electrical Power Engineer, User Terminals - TeraWave

Blue Origin Cupertino, California

FPGA DFT

18h

SoC Machine Learning Design Engineer

Apple Multiple Locations

RTL SOC

18h

SoC Machine Learning Design Engineer

Apple Multiple Locations

RTL SOC

18h

ASIC Design Engineering Lead - SoC IP DMA

Apple Sunnyvale, United States

ASIC RTL

18h

Senior Engineer, PLL Design

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

19h

Formal Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

19h

Principal Communications System Test Engineer - Verification and Validation

CesiumAstro Austin, Texas

FPGA Verification

19h

Senior Electrical Engineer, Hardware Platform, 8+ years of experience

Anduril Costa Mesa, California

FPGA DFT

19h

FPGA Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

19h

2027 Internship - Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog RTL

19h