today

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

1h

Physical Design Engineer

Intel Bangalore, India

ASIC RTL

1h

Physical Design Engineer

Intel Bangalore, India

ASIC RTL

1h

Senior SRAM Engineer

NVIDIA Santa Clara, California

Verilog Static Timing

2h

Senior Design Verification Engineer - PCIE

NVIDIA Multiple locations

SystemVerilog ASIC

2h

Software Verification Engineer

NVIDIA Israel, Raanana

Verification

2h

ASIC Verification Engineer - GPU

NVIDIA Multiple locations

Verilog System Verilog

2h

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

ASIC RTL

2h

ASIC Physical Design Intern - 2027

NVIDIA Hsinchu, Hsinchu

ASIC RTL

2h

IC Verification Engineer

Broadcom USA-California-San Jose-1320 Ridder Park Drive

Verilog System Verilog

2h

Design Engineer - STA

Broadcom USA-Colorado-Fort Collins-4380 Ziegler Road

ASIC STA

2h

SENIOR DESIGN ENGR

NXP Semiconductors Multiple locations

Verilog SystemVerilog

2h

Principal CAD Engineer Digital Verification

NXP Semiconductors Noida, Uttar Pradesh

Verilog System Verilog

2h

ASIC Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

FPGA ASIC

2h

Principal ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

2h

Technical Staff Engineer - Design

Microchip Technology Bangalore, India

Verilog System Verilog

2h

Principal Electrical Engineer

BAE Systems Hudson, New Hampshire

VHDL Verilog

2h

Systems Architecture, Integration, and Test Engineer (Test & Verification)

Saronic Austin, Texas

Verification

2h

Senior Electrical Engineer – PCBA Schematic & Layout

Saronic Austin, Texas

FPGA DFT

2h

Senior Staff Digital Design Engineer - Audio DSP Algorithm

Syntiant Bengaluru, Karnataka

Verilog System Verilog

2h

AMS Verification Engineer (RFIC Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

2h

AMS Verification Engineer (RFIC Engineering)

SpaceX Irvine, California

Verilog System Verilog

2h

Manufacturing Engineer - Data Center Hardware

Anthropic Remote-Friendly, United States

DFT Design for Test

3h

yesterday

Senior Digital Design - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

1d

Principal Layout Engineer

NXP Semiconductors Catania, Sicily

Digital Design DFT

1d

Principal Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

1d

Digital Verification Engineer

NXP Semiconductors Milan

SystemVerilog ASIC

1d

Digital Verification Engineer

NXP Semiconductors Milan

SystemVerilog ASIC

1d

Digital Designer F/M

NXP Semiconductors Toulouse, Occitanie

Digital Design STA

1d

Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

1d

Senior Firmware PHY Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

1d

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Logic Design

1d

ASIC Design Engineer - RTL and Circuits

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1d

Aug. 23, 2026

RTL Design Engineer

Intel Hillsboro, Oregon

Verilog System Verilog

2d

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

2d

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

2d

Aug. 22, 2026

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

3d

Principal Engineer -Technical Information

Microchip Technology Hyderabad, Telangana

FPGA RTL

3d

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

3d

Electrical Test Engineer III - TeraWave

Blue Origin Denver, Colorado

DFT Design for Test

3d

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

3d

Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

3d

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

3d

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

3d

Senior Principal Digital Engineer

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

3d

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

3d

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

3d

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

3d

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

3d

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

3d