today

CPU Circuit Design Engineer

Intel Austin, Texas

RTL STA

44m

CPU Core Physical Design Engineer

Intel Folsom, California

RTL Static Timing

44m

RTL Design Engineer

Intel Multiple locations

VHDL Verilog

44m

GPU Design Verification Engineer

Intel Folsom, California

Verilog System Verilog

44m

Lead Design Engineer, SoC Design

NXP Semiconductors Pune, Maharashtra

Digital Design Verification

53m

Senior Lead Engineer - STA

NXP Semiconductors Noida, Uttar Pradesh

STA DFT

53m

Senior/Principal verification Engineer

NXP Semiconductors Hyderabad, Telangana

SystemVerilog RTL

53m

Linux Software Engineer - System Manager

NXP Semiconductors Bucharest, Bucharest

VHDL HDL

53m

SoC Architect

NXP Semiconductors Pune, Maharashtra

RTL SOC

53m

SOC chip lead

NXP Semiconductors Pune, Maharashtra

RTL DFT

53m

Junior Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

53m

Senior QA Automation Engineer, ASIC Simulation

NVIDIA Ukraine, Kyiv; Ukraine, Remote; Greece, Remote

ASIC

1h

Senior Verification Engineer, SoC

NVIDIA Multiple locations

Verilog System Verilog

1h

DPU Performance Validation Engineer

NVIDIA Tel Aviv, Tel Aviv District

FPGA ASIC

1h

Senior Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

1h

GPU Core Pipeline IP Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1h

Senior Verification Engineer, Switch SoC

NVIDIA Bengaluru, Karnataka

Verilog UVM

1h

Architect – AI-Powered Performance Verification Automation

NVIDIA Bengaluru, Karnataka

SystemVerilog UVM

1h

ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog System Verilog

1h

Compiler Verification Engineer, Compute Performance – GPU

NVIDIA Multiple locations

Verification

1h

Manager for IO and Mixed Signal Design

Broadcom Singapore, Central Singapore

Static Timing Place and Route

1h

DFT Engineer

Broadcom San Jose, California

DFT Design for Test

1h

Senior Digital Design Engineer

CACI Multiple locations

VHDL Verilog

1h

Manager Digital Engineering 2

Northrop Grumman United States-Maryland-Baltimore

FPGA ASIC

1h

Senior Design Verification Engineer - TeraWave

Blue Origin Central Texas; Greater Seattle Area; Bay Area, CA

SystemVerilog ASIC

1h

Principal Emulation & Prototyping Engineer

Blue Origin San Diego, California

Verilog SystemVerilog

1h

Sr Principal Verification Engineer

Analog Devices Bangalore, India

Verilog SystemVerilog

1h

Staff Engineer, Physical Design

Analog Devices Multiple locations

RTL STA

1h

Video Codec Digital Circuit Design Engineer

Qualcomm Taipei, Taipei

ASIC RTL

1h

#Systems SoC Test Engineer

Qualcomm San Diego, California

SOC

1h

Formal Verification Engineer, Staff

Qualcomm Bangalore, India

Verification

1h

PD Engineer

Qualcomm Santa Clara, California

ASIC STA

1h

Senior Director SoC Architecture - AI Accelerators (Multiple Locations)

Qualcomm Multiple locations

ASIC Verification

1h

Senior SoC Platform Software Engineer

Qualcomm Zhubei City, Hsinchu City, Taiwan

SOC

1h

SoC Thermal Engineer

Qualcomm Bangalore, India

FPGA SOC

1h

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm Multiple locations

VHDL Verilog

1h

AI/ML Logic Design Engineer-Senior

Qualcomm Austin, Texas

SystemVerilog RTL

1h

FPGA Engineer - Hod HaSharon

Qualcomm Hod HaSharon, Central District

Verilog SystemVerilog

1h

CAD Engineer on ML/AI for Design Verification

Qualcomm San Diego, California

ASIC Verification

1h

CPU Server Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

1h

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm San Diego, California

ASIC RTL

1h

SoC Power Validation Engineer

Qualcomm San Diego, California

ASIC RTL

1h

Graphics Modelling Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1h

GPU Design Verification Engineer

Qualcomm Markham, Ontario

VHDL Verilog

1h

GPU Design Verification Engineer

Qualcomm Multiple locations

VHDL Verilog

1h

ASIC Design Engineer

Qualcomm Santa Clara, California

FPGA ASIC

1h

SOC Platform Architect

Qualcomm Multiple locations

SOC Verification

1h

NPU/AI Processor Architecture (RTL) design- Staff/Sr Staff

Qualcomm Bangalore, India

RTL Logic Design

1h

Systems Architecture, Senior to Staff – Agentic AI

Qualcomm Markham, Ontario

ASIC Synthesis

1h

Peripherals Design Verification -Sr Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1h