today

Engineering IP Program Manager, Principal

Marvell Bangalore, India

ASIC Design for Test

19h

Manager Digital Engineering 2

Northrop Grumman Multiple locations

FPGA ASIC

19h

Sr Principal FPGA Engineer

Northrop Grumman Cincinnati, Ohio

VHDL Verilog

19h

Sr Hardware Design Engineer

Blue Origin Greater Seattle Area

VHDL Verilog

19h

SoC Verification Engineer - Design for Debug/Design For Test

Intel Bangalore, India

Verilog System Verilog

20h

Digital Design Engineering Intern

Analog Devices Milan, Lombardy

Verilog SystemVerilog

20h

CPU Microarchitect / RTL Design Engineer

Apple Santa Clara, California

RTL Verification

20h

Senior Mixed Signal Design Engineer

NVIDIA Santa Clara, California

Verilog SystemVerilog

20h

Senior ASIC Design Engineer, Memory Controller

NVIDIA Santa Clara, California

Verilog System Verilog

20h

Senior ASIC Design Efficiency Engineer

NVIDIA Multiple locations

Verilog System Verilog

20h

Senior Verification Engineer - HSIO Unit Level

NVIDIA Multiple locations

FPGA UVM

20h

Senior Engineer, CAD

Micron Hyderabad, Telangana

STA Static Timing

20h

New College Grad - Design Engineer

Micron San Jose, California

Verilog SystemVerilog

20h

Software Development Engineer (FPGA Device Modeling)

Lattice Semiconductor Penang, Malaysia

FPGA RTL

20h

ASIC Implementation Engineer

Broadcom San Jose, California

ASIC RTL

20h

Design Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

20h

IC Design Engineer

Broadcom Multiple locations

ASIC STA

20h

CPLD/FPGA Engineer

HPE Juniper Networks Taipei, Taipei

FPGA

21h

yesterday

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

1d

Senior Principal FPGA Design Engineer

BAE Systems Austin, Texas

VHDL FPGA

1d

ASICS Design Verification Engineer- (Multiple Levels)

Qualcomm San Diego, California

SystemVerilog ASIC

1d

RFA Design Engineer, Senior

Qualcomm Bangalore, India

ASIC RTL

1d

NOC DV Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1d

DFT Engineer, Staff

Qualcomm Toronto, Ontario

VHDL Verilog

1d

Sr. Staff Hardware Design Engineer, SoC/SIP

Qualcomm Multiple locations

SOC

1d

Verification Engineer

Philips Shenyang, Liaoning

Verification

1d

Senior FPGA Verification Engineer

Anduril Boulder, Colorado

VHDL Verilog

1d

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

1d

Senior FPGA Verification Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1d

Senior Firmware Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1d

Senior Embedded Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1d

FPGA Verification Engineer II

CesiumAstro Westminster, Colorado

VHDL Verilog

1d

Lead PCB Designer (Starshield)

SpaceX Hawthorne, California

FPGA Digital Design

1d

Software Engineering Manager

Baya Systems Bengaluru, Karnataka

SOC IP Design

1d

Senior Engineer, Design Verification

Samsung Semiconductor San Jose, California

Verilog System Verilog

1d

Embedded Software Designer - AI Knowledge and Data

Fidus Systems Kitchener, Ontario

FPGA ASIC

1d

Embedded Software Designer - AI Agents and Tooling

Fidus Systems Kitchener, Ontario

FPGA ASIC

1d

Nov. 13, 2026

R&D Engineer Physical Design

Broadcom San Jose, California

STA Static Timing

2d

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

2d

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

2d

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

2d

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

2d

Principal Physical Design Engineer — ASIC Products Division (APD)

Broadcom San Jose, California

ASIC STA

2d

Senior Microarchitecture and Design Engineer - AI SoC

Intel Bangalore, India

SystemVerilog RTL

2d

Senior Formal Verification Engineer

Intel Bangalore, India

Verilog System Verilog

2d

Principal Engineer - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

2d

Senior ATE Hardware Engineer

Lattice Semiconductor Penang, Malaysia

FPGA DFT

2d

Digital Hardware Engineer

BAE Systems Nashua, New Hampshire

FPGA Digital Design

2d

Mixed Signal Design Engineer Intern

Analog Devices Bari, Apulia

Verilog SystemVerilog

2d

Memory Design Engineer

Allegro MicroSystems Milan, Lombardy

Verilog SystemVerilog

2d