today

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

18h

Principal Engineer -Technical Information

Microchip Technology Hyderabad, Telangana

FPGA RTL

18h

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

18h

Electrical Test Engineer III - TeraWave

Blue Origin Denver, Colorado

DFT Design for Test

18h

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

18h

Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

18h

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

18h

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

18h

Senior Principal Digital Engineer

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

18h

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

19h

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

19h

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

19h

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

19h

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

19h

Physical Design Power Optimization and Modeling Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

19h

Senior Architecture Energy Modeling Engineer

NVIDIA Santa Clara, California

Verilog ASIC

19h

Architecture Energy Modeling Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog ASIC

19h

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

RTL Verification

19h

Sr. Staff SoC Power & Performance Architect

Ambiq Micro, Inc. Austin, Texas

19h

Senior Electrical Engineer I/II

Rocket Lab Pasadena, California

Verilog FPGA

19h

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

19h

yesterday

Electrical Engineering Intern (Summer 2027)

Second Order Effects Multiple Locations

VHDL Verilog

1d

Electrical Engineering Intern (Spring 2027)

Second Order Effects Multiple Locations

VHDL Verilog

1d

Embedded Engineer

Second Order Effects El Segundo, California

Verilog FPGA

1d

Embedded Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

1d

Electrical Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

1d

Electrical Engineer

Second Order Effects El Segundo, California

Verilog FPGA

1d

Staff Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

1d

Senior Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

1d

Senior STA Signoff Methodology Engineer

NVIDIA Multiple locations

ASIC STA

1d

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1d

Digital Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

FPGA Design Engineer (Level 3 or 4)

Northrop Grumman United States-Maryland-Linthicum

1d

Electrical Engineer – Integrated Analog/Digital Design Level 3 /4

Northrop Grumman United States-California-Sunnyvale

1d

Principal/ Sr. Principal FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal/ Sr. Principal Digital Verification Engineer

Northrop Grumman United States-California-San Diego

1d

Principal FPGA/Sr. Principal FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal Digital/Sr. Principal Digital Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal/Sr. Principal Digital Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal/Sr. Principal Digital Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal/Sr. Principal FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Principal Systems Engineer - Requirements & Verification

Northrop Grumman Multiple Locations

1d

Electrical Engineer FPGA - Level 3/4 - Dulles

Northrop Grumman United States-Virginia-Dulles

1d

FPGA Manager 2

Northrop Grumman United States-Illinois-Rolling Meadows

1d

Sr. Principal Digital Design Verification Lead

Northrop Grumman United States-California-San Diego

1d

FPGA Verification Engineer Level 3/4 - Linthicum

Northrop Grumman United States-Maryland-Linthicum

1d

FPGA Verification Engineer Level 5 - Linthicum

Northrop Grumman United States-Maryland-Linthicum

1d

Principal Engineer ASIC or Sr Principal Engineer ASIC

Northrop Grumman United States-California-Manhattan Beach

1d

Principal Systems Engineer - Requirements & Verification

Northrop Grumman Multiple Locations

1d

FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

1d