yesterday

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

1d

VLSI Integration Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

1d

Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

Verilog System Verilog

1d

Senior Software Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

1d

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

1d

Physical Design STA CAD Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Static Timing

1d

Director of Physical Design

Ambiq Micro, Inc. Austin, Texas

RTL Synthesis

1d

Principal Physical Verification Engineer

Celero Communications, Inc. San Jose, California

Verification

1d

Principal Physical Design Engineer

Celero Communications, Inc. San Jose, California

ASIC RTL

1d

Principal Analog Mixed Signal ASIC Layout Engineer

Draper Cambridge, Massachusetts

ASIC Verification

1d

Microelectronics Integration and Test Engineer

Draper Cambridge, Massachusetts

ASIC Design for Test

1d

Mixed Signal Design Verification Engineer

Intel Bangalore, India

Verilog System Verilog

1d

Graduate FPGA Engineer (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

1d

FPGA Internship (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

1d

Senior NVM Digital Designer

Mythic AI Palo Alto, California

Verilog SystemVerilog

1d

Senior Mixed Signal / Memory Circuit Designer

Mythic AI Palo Alto, California

Verilog System Verilog

1d

Software Engineer - FPGA-Accelerated RTL Simulation

SiFive Berkeley, California

FPGA ASIC

1d

Digital Verification Engineer - MCU

NXP Semiconductors Catania, Sicily

SystemVerilog UVM

1d

Aug. 17, 2026

Senior Staff RTL Design /Verification

Marvell IL - Petah Tikva; Yokneam

SystemVerilog RTL

1d

DFT Principal Engineer

Marvell Petah-Tikva; Yokneam

Verilog SystemVerilog

1d

Design Verification, Manager

Marvell Ho Chi Minh City, Hồ Chí Minh

SystemVerilog UVM

1d

Design Verification Senior Staff Engineer

Marvell IL - Petah Tikva

Verilog SystemVerilog

1d

Senior Manager, ASIC Design

Marvell Santa Clara, California

Verilog SystemVerilog

1d

Staff to Senior Staff Engineer, DFT

Marvell Bangalore, India

RTL STA

1d

DSP Firmware Engineer

Marvell Cordoba, Argentina

Verilog SystemVerilog

1d

Principal Engineer, Verification

Marvell Santa Clara, California

Verilog System Verilog

1d

Principal Engineer - Digital IC Design

Marvell Bangalore, India

Verilog ASIC

1d

Principal Design Verification Engineer

Marvell Bangalore, India

Verilog System Verilog

1d

Senior Principal Engineer, Design Verification

Marvell Ottawa, Ontario

Verilog System Verilog

1d

DFT Manager

Marvell Ottawa, Ontario

ASIC RTL

1d

Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon

Marvell Santa Clara, California

RTL SOC

1d

Hardware & Silicon Validation Senior Staff Engineer

Marvell Santa Clara, California

ASIC Digital Design

1d

Principal Test Engineer (Optical Module)

Marvell Santa Clara, California

ASIC DFT

1d

Analog Design - Senior Principal Engineer

Marvell Bangalore, India

RTL DFT

1d

Senior Staff Digital Design Engineer

Marvell Ottawa, Ontario

Verilog System Verilog

1d

Design/DSP/Verification Intern - PhD Degree

Marvell Santa Clara, California

SOC

1d

Principal Verification Engineer

Marvell Santa Clara, California

Verilog System Verilog

1d

Principal AMS verification engineer

Marvell Bangalore, India

Verilog Verification

1d

Physical Design Intern

Marvell Cordoba, Argentina

ASIC Static Timing

1d

Senior / Staff Verification Engineer - RF/TIA (Analog Mixed Signal)

Marvell Singapore, Central Singapore

Verilog Verification

1d

Design Verification Engineer - Early Career

Marvell Multiple locations

VHDL Verilog

1d

Principal Engineer - PCIe RTL Design

Marvell Bangalore, India

Verilog SystemVerilog

1d

Design Verification Engineer

Marvell IL - Petah Tikva; Yokneam

Verilog System Verilog

1d

Senior Principal Memory Architect

Marvell Multiple locations

ASIC RTL

1d

Senior Staff Verification Engineer

Marvell Pune, Maharashtra

SystemVerilog UVM

1d

Digital IC Design Senior Staff Engineer

Marvell Petah-Tikva

Verilog SystemVerilog

1d

Senior Design Engineer

Marvell Petah-Tikva

Verilog SystemVerilog

1d

Design Verification Senior Staff Engineer

Marvell Petah-Tikva

SystemVerilog ASIC

1d

Principle Verification Engineer

Marvell IL - Petah Tikva

SystemVerilog ASIC

1d

Technical Lead IC Design/Principal - Micro-architecture, RTL Design

Marvell Ottawa, Ontario

Verilog System Verilog

1d