today

Design Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

17h

IC Verification Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog System Verilog

17h

Senior QA/DV Program Manager

Axiado Hyderabad, Telangana

FPGA ASIC

17h

Library Characterization Engineer

Microchip Technology Rousset, Provence-Alpes-Côte-d’Azur

STA Place and Route

17h

Principle Engineer - CAD (Physical Verification)

Microchip Technology Chandler, Arizona

FPGA ASIC

17h

INTERN_NVE Design Eng

Micron Avezzano, Abruzzo

VHDL Verilog

17h

INTERN_NVE Design Eng

Micron Avezzano, Abruzzo

VHDL Verilog

17h

Design Engineer

Micron Avezzano, Abruzzo

Verilog RTL

17h

Senior DFT Engineer - Post Silicon

NVIDIA Multiple locations

DFT

17h

Senior Software Engineer - SOC Platforms

NVIDIA Santa Clara, California

SOC

17h

Microarchitecture and Design Engineer - AI SoC

Intel Multiple locations

SystemVerilog RTL

18h

SOC RTL Design Engineer

Intel Multiple locations

SystemVerilog RTL

18h

SOC Design Verification Engineer

Intel Multiple locations

RTL Register Transfer

18h

IP Design - Staff engineer

Qualcomm Chennai, Tamil Nadu

Verilog RTL

18h

GPU Design Verification Engineer

Qualcomm Boxborough, Massachusetts

VHDL Verilog

18h

Pre-Silicon Validation Engineer

Qualcomm San Diego, California

SystemVerilog FPGA

18h

CPU Server Physical Design Engineer, Santa Clara

Qualcomm Santa Clara, California

VHDL Verilog

18h

FY27 Intern - Digital Design Intern - Hod Hasharon

Qualcomm Hod HaSharon, Central District

Verilog System Verilog

18h

Security System Test Engineer

Qualcomm San Diego, California

ASIC SOC

18h

Engineer, SoC Performance

Qualcomm Bangalore, India

FPGA SOC

18h

STA Engineer, Associate

Qualcomm Bangalore, India

FPGA Verification

18h

SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team

Qualcomm Bangalore, India

FPGA ASIC

18h

Design Verification Engineer - NPU- Engineer to Sr. Staff Engineer

Qualcomm Austin, Texas

ASIC Verification

18h

Performance Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr.Staff

Qualcomm Austin, Texas

RTL SOC

18h

SoC Design Implementation Engineer

Qualcomm Hyderabad, Telangana

FPGA RTL

18h

Physical Design Engineer, Staff - Hod Hasharon

Qualcomm Hod HaSharon, Central District

ASIC STA

18h

ASIC Design Engineer, Low Power Audio AI Subsystems

Qualcomm Markham, Ontario

VHDL Verilog

18h

Foundry Engineer for Advanced Technology (Device/Process/ Product)

Qualcomm Hsinchu City, Taiwan

ASIC SOC

18h

Digital Circuit Design Engineer

Apple Austin, Texas

Verilog SystemVerilog

18h

FE Engineering

Apple Austin, Texas

Verilog System Verilog

18h

FE Engineer

Apple Austin, Texas

Verilog RTL

18h

FE Engineer

Apple Cupertino, California

Verilog System Verilog

18h

Design for Test Engineer

Apple Austin, Texas

Verilog RTL

18h

Design Verification Engineer

Apple Austin, Texas

SystemVerilog RTL

18h

FE Engineer

Apple Cupertino, California

Verilog System Verilog

18h

Design Verification Engineer

Apple Cupertino, California

Verilog SystemVerilog

18h

FE Engineer

Apple Austin, Texas

Verilog System Verilog

18h

VLSI CAD Engineer

Apple Cupertino, California

RTL Register Transfer

18h

FPGA Design Engineer, Senior Principal

BAE Systems Multiple locations

VHDL Verilog

18h

Next Generation SoC Integration Solution Lead

NXP Semiconductors Noida, Uttar Pradesh

FPGA RTL

18h

Senior PCB Layout Engineer

Blue Origin Cupertino, California

FPGA Digital Design

18h

Lidar FPGA Engineer - Lunar Permanence

Blue Origin Denver, Colorado

VHDL Verilog

18h

Manager Digital Engineering 3

Northrop Grumman Manhattan Beach, California

FPGA ASIC

18h

Principal Engineer Digital FPGA/Sr. Principal Engineer Digital FPGA (Level 3/4)

Northrop Grumman Manhattan Beach, California

FPGA

18h

Principal Engineer, PHY/MAC Design (P)

InnoPhase IoT San Jose, California

Verilog SystemVerilog

19h

Sr. RF Silicon Software Engineer (RFIC Engineering)

SpaceX Redmond, Washington

SystemVerilog FPGA

19h

DFT Intern

Ambiq Micro, Inc. Singapore, Central Singapore

VHDL Verilog

19h

Staff Analog/Mixed Signal Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

19h

yesterday

Integrated Circuits Intern

Draper Cambridge, Massachusetts

Verilog System Verilog

1d

Electrical Engineering Intern, Summer 2027

BAE Systems Multiple locations

FPGA Digital Design

1d