today

Blue Ring Mission Systems Requirements & Verification Engineer

Blue Origin Greater Seattle Area

Verification

3m

Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave

Blue Origin San Diego, California

Verilog SystemVerilog

3m

Avionics Hardware Engineer

Blue Origin Multiple locations

FPGA Design for Test

3m

Senior Electrical Engineer – TeraWave High-Speed Digital & Networking Payload Hardware

Blue Origin Greater Seattle Area

FPGA DFT

3m

Aerospace Systems Engineer III - Blue Ring Space Vehicle Requirements & Verification Architect (MTN)

Blue Origin Multiple locations

Verification

4m

Sr. Manufacturing PCBA Design & SMT Fab DFX Engineer

Blue Origin Bay Area, CA; Greater Seattle Area

FPGA ASIC

4m

Senior Manufacturing Opto-Mechanical & Sensor DFX Engineer

Blue Origin Bay Area, CA

DFT Design for Test

4m

Sr. Senior Manufacturing Surface Treatment, Sealing & Adhesion DFX Engineer

Blue Origin Bay Area, CA

DFT Design for Test

4m

Senior Electrical Engineer - Power Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

4m

Senior Electrical Engineer - Circuit Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

4m

RFIC Layout Engineer

Apple Multiple Locations

RTL SOC

16m

GPU IP Verification Engineer

Intel Bangalore, India

VHDL Verilog

17m

GPU IP Integration Model Build Engineer

Intel Bangalore, India

UVM OVM

17m

Senior PDK Support Engineer (Physical Verification)

Intel Multiple locations

SOC Verification

17m

CPU Circuit Design Engineer

Intel Bangalore, India

Verilog Digital Design

17m

Senior Engineer II - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

33m

Senior Principal FPGA Verification Engineer - $30K Sign-On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

38m

Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Multiple locations

Verilog SystemVerilog

39m

Cyber Security Operations Analyst (Tier 2 SOC)

Marvell Bangalore, India

SOC

39m

Summer Program Intern

Marvell Cordoba, Argentina

Verilog Digital Design

39m

Electrical Engineer

CACI Florham Park, NJ, US

VHDL Verilog

41m

Electrical Engineer

CACI Florham Park, NJ, US

VHDL Verilog

41m

Embedded Systems Engineer

CACI San Antonio, Texas

VHDL Verilog

41m

Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1h

Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1h

Physical Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

1h

Senior FPGA Verification Engineer

Anduril Boulder, Colorado

VHDL Verilog

1h

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

1h

Senior FPGA Verification Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1h

Senior Firmware Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1h

Senior Embedded Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1h

Design Verification Engineer - Compute

MatX Mountain View, California

Remote SystemVerilog UVM

1h

yesterday

Principal FPGA Designer – TeraWave

Blue Origin Greater Seattle Area

VHDL Verilog

23h

Senior Engineer, Digital Design Engineering

Analog Devices Egypt, New Cairo

SystemVerilog FPGA

23h

GPU IP Lead Emulation Model Build Engineer

Intel Bangalore, India

FPGA RTL

23h

Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

23h

Junior CPU Verification Engineer

Intel Multiple locations

Verilog System Verilog

23h

​​Digital Signal Processing Engineer​

Semtech Meylan, Auvergne-Rhône-Alpes

SystemVerilog RTL

1d

Engineering Intern (EE/CE/RF) III, Summer 2027 (Hybrid)

BAE Systems Nashua, New Hampshire

VHDL Verilog

1d

FPGA Engineer

Philips Suzhou

VHDL Verilog

1d

Senior Power Architect, SoC Power and Thermal Management SW

NVIDIA Santa Clara, California

SOC

1d

Senior System Integration and Validation Engineer

NVIDIA Santa Clara, California

Logic Design DFT

1d

ASIC Design Engineer – Clocks IP

NVIDIA Multiple locations

Verilog ASIC

1d

Formal Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1d

Senior System Level Testability Engineer

NVIDIA Santa Clara, California

Digital Design SOC

1d

ASIC Design Engineer - New College Grad 2026

NVIDIA Santa Clara, California

VHDL Verilog

1d

Senior Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1d

Principal Engineer - Layout

Microchip Technology Allentown, Pennsylvania

Place and Route Synthesis

1d

Senior Technical Staff Engineer - SOC Verification

Microchip Technology Chandler, Arizona

SystemVerilog RTL

1d

Technical Safety Assessor / Architect (HW- Soc) (f/m/d)

NXP Semiconductors Toulouse, Occitanie

SOC Verification

1d