today

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

SystemVerilog RTL

48m

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

48m

FPGA Design Engineer Level 2

Northrop Grumman United States-Maryland-Linthicum

VHDL Verilog

59m

Engineer/Principal Engineer Digital-RF Subsystems I&T

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

59m

Principal Engineer/Sr. Principal Engineer Digital-RF Subsystems I&T Lead

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

59m

R10230854 Principal/ Senior Principal Hardware/Firmware CAM

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

59m

DMA designer, up to Staff

Qualcomm Taipei, Taipei

SystemVerilog ASIC

1h

Modem Hardware Design Verification Engineer – AI Driven Next Gen Modem Hardware Development, Staff

Qualcomm Boxborough, Massachusetts

VHDL Verilog

1h

DDR STA/Timing Engineer (Staff/ Senior Staff)

Qualcomm Bangalore, India

FPGA ASIC

1h

GPU Design Engineer

Qualcomm Austin, Texas

Verilog SystemVerilog

1h

NPU/AI Processor Synthesis Sr Staff Engineer

Qualcomm Bangalore, India

ASIC RTL

1h

ASIC 3D DRAM Architect

Qualcomm Seoul, Seoul

Verilog ASIC

1h

Mixed Signal Design Verification Engineer

Qualcomm San Diego, California

SystemVerilog ASIC

1h

CPU Micro-architect/RTL Designer

Qualcomm Multiple locations

VHDL Verilog

1h

FY27 Intern - Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

VHDL Verilog

1h

Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm San Diego, California

ASIC RTL

1h

Serdes PHY Analog Design Engineer

Qualcomm Bangalore, India

FPGA RTL

1h

Camera IP Verification - Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

1h

SOC Design Verification Engineer-Staff

Qualcomm San Diego, California

ASIC RTL

1h

Display Synthesis Engineer, Sr Lead

Qualcomm Bangalore, India

RTL STA

1h

CPU Post Silicon Power and Performance Engineer, Senior/Staff - Cork, Ireland

Qualcomm Cork, Munster

ASIC SOC

1h

CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm Multiple locations

VHDL Verilog

1h

Physical Design Engineer

Marvell Cordoba, Argentina

ASIC RTL

1h

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

1h

Functional Validation Intern, BS - Summer 2027

Marvell Multiple locations

FPGA ASIC

1h

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

1h

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

1h

Physical Design Engineer Intern, BS - Summer 2027

Marvell Multiple locations

ASIC RTL

1h

Physical Design Engineer Intern, MS - Summer 2027

Marvell Multiple locations

ASIC RTL

1h

Digital Design Engineer

Silicon Labs Oslo

VHDL Verilog

1h

Senior System Integration and Validation Engineer

NVIDIA Bengaluru, Karnataka

Logic Design DFT

1h

Senior Networking ASIC Functional Characterization Engineer

NVIDIA Israel, Yokneam

ASIC

1h

Senior ASIC Engineer, Switch SoC

NVIDIA Bengaluru, Karnataka

Verilog ASIC

1h

ASIC Design and Verification Intern, SOC - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

1h

SOC Design Team Methodology Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC SOC

1h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

1h

Intel NPU Internship

Intel Leixlip, Leinster

FPGA RTL

1h

Firmware Engineer for Phased Array Communication Ground Systems

AeroVironment Albuquerque, New Mexico

FPGA ASIC

1h

Digital Eng (SoC RTL)

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1h

Sr Design Verification Eng

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1h

Senior Engineer, Post Silicon Validation

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1h

Silicon Validation Engineer

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1h

Staff Engineer - Post Siiicon Validation

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1h

Senior Manager, Post-Silicon Validation Engineering

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1h

Sr. Staff Engineer, Front-End Verification

Tenstorrent Multiple locations

SystemVerilog RTL

2h

Sr. Engineer, SoC Design Verification, PCIe

Tenstorrent Boston, Massachusetts

RTL UVM

2h

Hardware Engineer (FPGA)

Virtu Financial Dublin, Leinster

VHDL SystemVerilog

2h

Principal Electrical Engineer

Rocket Lab Chantilly, Virginia

FPGA ASIC

2h

Principal Electrical Engineer

Rocket Lab Tucson, Arizona

FPGA ASIC

2h

yesterday

Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1d