today

R&D Engineer Hardware 4

Broadcom Chandler, Arizona

STA Static Timing

11h

Ethernet NIC System Architecture

Broadcom Multiple locations

Verilog SystemVerilog

11h

DFT Lead Engineer

Broadcom Austin, Texas

Verilog ASIC

11h

DFT Engineer

Broadcom Austin, Texas

Verilog ASIC

11h

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

11h

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

11h

DFT Engineer

Broadcom Austin, Texas

Verilog ASIC

11h

ASIC Verification Engineer

Broadcom Multiple locations

Verilog SystemVerilog

11h

ASIC Emulation & Verification Engineer

Broadcom San Jose, California

Verilog SystemVerilog

11h

ASIC Emulation and Verification Engineer

Broadcom San Jose, California

Verilog SystemVerilog

11h

SRAM Design Lead

Micron Multiple locations

Verilog RTL

11h

Graduate Talent (SoC Functional Validation)

Intel Penang, Malaysia

ASIC

11h

Graduate Talent (SoC Functional Validation)

Intel Penang, Malaysia

Verilog SystemVerilog

11h

Graduate Talent (SoC Functional Validation)

Intel Penang, Malaysia

FPGA ASIC

11h

SOC Functional Validation Engineer

Intel Bangalore, India

RTL SOC

11h

SoC Validation Engineer – Power Management

Intel Multiple locations

SystemVerilog RTL

11h

Graduate Talent (SoC Functional Validation)

Intel Penang, Malaysia

ASIC Digital Design

11h

Power Delivery Integration and Power Rail Stress Engineer- SoC Power Thermal Performance Validation Engineer (Temporary position)

Intel Guadalajara, Jalisco

SOC Verification

11h

Power Thermal Validation and Power Management Engineer - SoC Power Thermal Performance Validation (Temporary position)

Intel Guadalajara, Jalisco

SOC Verification

11h

Staff Design Engineer

Lattice Semiconductor Penang, Malaysia

FPGA ASIC

11h

Staff Software Development Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

11h

Software Development Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

11h

Senior ASIC Engineer

NVIDIA Shanghai, Shanghai

ASIC RTL

12h

Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

12h

Senior Digital Design Verification Engineer - Hardware

NVIDIA Santa Clara, California

SystemVerilog RTL

12h

Principal Analog Design Engineer (Data-Converters)

NXP Semiconductors Multiple locations

Verilog SOC

12h

Verification & Validation Technician

Philips New Kensington, Pennsylvania, United States

Verification

12h

Physical Design Engineer, ML4PD

Tenstorrent Austin, Texas

ASIC RTL

13h

DFT Engineer

Tenstorrent Multiple locations

Verilog SystemVerilog

13h

Electronics Development Engineer

HRL Laboratories Malibu, CA,US

FPGA ASIC

13h

Principal SoC Development Platform Engineer

Cirrus Logic Austin, Texas

FPGA RTL

13h

Sr/Staff Digital Design Engineer

Lightmatter Toronto, Ontario

Verilog SystemVerilog

13h

Sr/Staff Digital Design Engineer

Lightmatter Boston, Massachusetts

Verilog SystemVerilog

13h

Sr/Staff Digital Design Engineer

Lightmatter Mountain View, California

Verilog SystemVerilog

13h

yesterday

Backend Physical Design Engineer

Broadcom IND-Bangalore Electronic City - S1

Digital Design STA

1d

Principal FPGA Micro-Architect

Lattice Semiconductor San Jose, California

Verilog SystemVerilog

1d

VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

Verilog System Verilog

1d

FPGA Designer - TeraWave RF and Optical Systems Firmware

Blue Origin Greater Seattle Area

VHDL Verilog

1d

Principal FPGA Designer – TeraWave

Blue Origin Greater Seattle Area

VHDL Verilog

1d

Sr ASIC Design Engineer - TeraWave

Blue Origin Multiple locations

VHDL Verilog

1d

Principal Engineer, HIG-HBM Product System Engineering (Media Health Manufacturing)

Micron Singapore, Central Singapore

Verilog DFT

1d

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing)

Micron Singapore, Central Singapore

Verilog DFT

1d

SoC Power Thermal Performance Val and Opt Engineer (Temporary Position)

Intel Guadalajara, Jalisco

1d

GPU Validation Engineer

Intel Toronto, Ontario

Verilog System Verilog

1d

Principal Electrical Engineer

BAE Systems Dallas, Texas

VHDL Verilog

1d

Senior Engineer II - Layout

Microchip Technology San Jose, California

ASIC SOC

1d

Senior SoC Architect, RAS

NVIDIA Multiple locations

RTL Design for Test

1d

Power Engineer

Apple Cupertino, California

RTL Logic Design

1d

FE Engineer

Apple San Diego, California

Verilog SystemVerilog

1d

Power Engineer

Apple Cupertino, California

ASIC RTL

1d