today

Senior Digital Design - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

18h

Principal Layout Engineer

NXP Semiconductors Catania, Sicily

Digital Design DFT

18h

Principal Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

18h

Digital Verification Engineer

NXP Semiconductors Milan

SystemVerilog ASIC

18h

Digital Verification Engineer

NXP Semiconductors Milan

SystemVerilog ASIC

18h

Digital Designer F/M

NXP Semiconductors Toulouse, Occitanie

Digital Design STA

18h

Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

18h

Senior Firmware PHY Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

18h

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Logic Design

18h

ASIC Design Engineer - RTL and Circuits

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

18h

yesterday

RTL Design Engineer

Intel Hillsboro, Oregon

Verilog System Verilog

1d

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

1d

ASIC Design Engineer – DSP / Analog / SerDes

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

1d

Aug. 22, 2026

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

2d

Principal Engineer -Technical Information

Microchip Technology Hyderabad, Telangana

FPGA RTL

2d

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

2d

Electrical Test Engineer III - TeraWave

Blue Origin Denver, Colorado

DFT Design for Test

2d

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

2d

Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

2d

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

2d

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

2d

Senior Principal Digital Engineer

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

2d

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

2d

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

2d

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

2d

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

2d

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

2d

Physical Design Power Optimization and Modeling Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

2d

Senior Architecture Energy Modeling Engineer

NVIDIA Santa Clara, California

Verilog ASIC

2d

Architecture Energy Modeling Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog ASIC

2d

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

RTL Verification

2d

Sr. Staff SoC Power & Performance Architect

Ambiq Micro, Inc. Austin, Texas

2d

Senior Electrical Engineer I/II

Rocket Lab Pasadena, California

Verilog FPGA

2d

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

2d

Aug. 21, 2026

Electrical Engineering Intern (Summer 2027)

Second Order Effects Multiple Locations

VHDL Verilog

3d

Electrical Engineering Intern (Spring 2027)

Second Order Effects Multiple Locations

VHDL Verilog

3d

Embedded Engineer

Second Order Effects El Segundo, California

Verilog FPGA

3d

Embedded Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

3d

Electrical Engineer

Second Order Effects Redmond, Washington

Verilog FPGA

3d

Electrical Engineer

Second Order Effects El Segundo, California

Verilog FPGA

3d

Staff Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

3d

Senior Electrical Engineer (High Speed Digital)

Second Order Effects El Segundo, California

FPGA ASIC

3d

Senior STA Signoff Methodology Engineer

NVIDIA Multiple locations

ASIC STA

3d

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

3d

Digital Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

3d

FPGA Design Engineer (Level 3 or 4)

Northrop Grumman United States-Maryland-Linthicum

3d

Electrical Engineer – Integrated Analog/Digital Design Level 3 /4

Northrop Grumman United States-California-Sunnyvale

3d

Principal/ Sr. Principal FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

3d

Principal/ Sr. Principal Digital Verification Engineer

Northrop Grumman United States-California-San Diego

3d

Principal FPGA/Sr. Principal FPGA Design Engineer

Northrop Grumman United States-Illinois-Rolling Meadows

3d