yesterday

Design Verification- Intern

Marvell IL - Petah Tikva

Verilog System Verilog

1d

Intern, RTL Power Macromodeling Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

1d

Intern, Power-Thermal Simulation Software Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

1d

PCB Designer (Starlink)

SpaceX Redmond, Washington

FPGA Digital Design

1d

DFT Engineer (CE-64000845)

Cirrus Logic Austin, Texas

VHDL Verilog

1d

2027 Internship - Formal Verification Engineer

Cirrus Logic Austin, Texas

Verilog System Verilog

1d

Junior Emulation Engineer

Celero Communications, Inc. Córdoba, Córdoba

Verilog SystemVerilog

1d

Solutions Architect, DSP/Algorithms

Fidus Systems Remote

Remote FPGA ASIC

1d

Solutions Architect, AI/ML

Fidus Systems Remote

Remote FPGA ASIC

1d

Solutions Architect, AI/ML

Fidus Systems Remote

Remote FPGA ASIC

1d

Staff FPGA Operations Project Engineer

CesiumAstro El Segundo, California

FPGA

1d

Staff FPGA Operations Project Engineer

CesiumAstro Austin, Texas

FPGA

1d

Staff FPGA Operations Project Engineer

CesiumAstro Westminster, Colorado

FPGA

1d

Oct. 27, 2026

STA - Lead Engineer

Qualcomm Chennai, Tamil Nadu

STA Synthesis

2d

Verification Engineer, Senior

Qualcomm Toronto, Ontario

SystemVerilog ASIC

2d

Physical Design - Engineer

Qualcomm Chennai, Tamil Nadu

STA Place and Route

2d

MSIP Design Verification Engineer - Cork, Ireland

Qualcomm Cork, Munster

Verilog SystemVerilog

2d

Senior GPU DV Engineer

Qualcomm San Diego, California

Verilog System Verilog

2d

Principal Engineer

Qualcomm Bangalore, India

ASIC RTL

2d

ASIC Architect - Hod Hasharon

Qualcomm Hod HaSharon, Central District

ASIC SOC

2d

CPU Design Verification Sr Lead Engineer

Qualcomm Hyderabad, Telangana

Verilog System Verilog

2d

Si GPU Functional Debug - Sr Engineer

Qualcomm Bangalore, India

FPGA RTL

2d

Digital Hardware Engineer, Senior

Qualcomm San Diego, California

VHDL Verilog

2d

Low Power Design/Methodology Engineer

Qualcomm Tijuana, Baja California

Verilog System Verilog

2d

HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)

Qualcomm San Diego, California

ASIC RTL

2d

Physical Design Staff Engineer

Qualcomm Noida, Uttar Pradesh

ASIC STA

2d

Emulation Engineer

Intel Virtual India

Verilog RTL

2d

Silicon Design Verification Engineer

Intel Bangalore, India

Verilog SystemVerilog

2d

SoC Logic Design Engineer

Intel Santa Clara, California

Verilog System Verilog

2d

GPU Validation Engineer

Intel Toronto, Ontario

UVM SOC

2d

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

2d

Senior Verification Engineer - CPU

NVIDIA Multiple locations

SystemVerilog UVM

2d

In-Order Tile TestBench Design Verification Engineer

SiFive Hyderabad, Telangana

SystemVerilog ASIC

2d

NCG Digital Design Engineer

Micron Jalisco, Chiapas

VHDL Verilog

2d

Apply now. India Campus Team!

Micron Hyderabad, Telangana

ASIC SOC

2d

Staff Datapath Design Engineer

Micron San Jose, California

Verilog System Verilog

2d

New College Grad - HBM VERIFICATION

Micron Jalisco, Chiapas

Verilog RTL

2d

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

FPGA ASIC

2d

Hardware Board Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

2d

Lead Engineer, Development Product Engineering

Allegro MicroSystems Alabang, Muntinlupa City, Philippines

DFT Design for Test

2d

Senior Signal Processing and Algorithm Engineer

Analog Devices Multiple locations

RTL Digital Design

2d

Principal Electrical Engineer, Mixed-Signal & Compute Systems (OISL Payload) - TeraWave

Blue Origin Greater Seattle Area

FPGA HDL

2d

Power Regulator Responsible Engineer, Project Sunrise

Blue Origin Longmont, Colorado

FPGA ASIC

2d

Senior PCB Layout Engineer

Blue Origin Multiple locations

FPGA Digital Design

2d

Engineer II - Verification

Microchip Technology Chandler, Arizona

Verilog System Verilog

2d

Logic Design Engineer

NXP Semiconductors Kanata

Verilog RTL

2d

Senior Staff Engineer Electronics Architect

Northrop Grumman Woodland Hills, California

VHDL Verilog

2d

Staff EDA Engineer

Lattice Semiconductor Pune, Maharashtra

FPGA RTL

2d

Lead STA Engineer

Broadcom Pune, Maharashtra

RTL STA

2d

Lead Physical Design Engineer

Broadcom Pune, Maharashtra

RTL Synthesis

2d