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Front-End CAD Engineer

Etched

Cupertino , California , United States

ASIC RTL DFT

Posted July 22, 2026

Emulation Software Engineer

Etched

Cupertino , California , United States

Verilog SystemVerilog ASIC

Posted July 22, 2026

ASIC Timing Engineer

Etched

Cupertino , California , United States

ASIC RTL STA

Posted July 22, 2026

Senior Hardware Engineer - Micro-Architect

quadric, Inc

Burlingame , California , United States

Verilog SystemVerilog FPGA

Posted July 22, 2026

Design Verification Intern

quadric, Inc

Burlingame , California , United States

Verilog SystemVerilog RTL

Posted July 22, 2026

FPGA Engineer

Astranis

San Francisco , California , United States

Verilog SystemVerilog FPGA

Posted July 22, 2026

Hardware Engineer (FPGA/ASIC)

Jane Street

New York, New York, United States

VHDL Verilog FPGA

Posted July 22, 2026

ASIC Physical Design Engineer

Jane Street

New York, New York, United States

ASIC RTL

Posted July 22, 2026

ASIC Physical Design Engineer

Jane Street

London , England , United Kingdom

ASIC RTL

Posted July 22, 2026

ASIC Engineer

Jane Street

New York, New York, United States

FPGA ASIC RTL

Posted July 22, 2026

ASIC Engineer

Jane Street

London , England , United Kingdom

FPGA ASIC RTL

Posted July 22, 2026

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic

Multiple Locations

FPGA ASIC RTL

Posted July 22, 2026

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies

Los Angeles , California , United States

FPGA ASIC RTL

Posted July 22, 2026

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies

Irvine , California , United States

FPGA ASIC RTL

Posted July 22, 2026

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies

Irvine , California , United States

Verilog FPGA ASIC

Posted July 22, 2026

FPGA Design Engineer

Silvus Technologies

Irvine , California , United States

FPGA ASIC RTL

Posted July 22, 2026

FPGA Design Engineer

Silvus Technologies

Los Angeles , California , United States

FPGA ASIC RTL

Posted July 22, 2026

Verification Engineer

Tenstorrent

Japan

Verilog

Posted July 22, 2026

Technical Program Manager, Architecture

Tenstorrent

Santa Clara , California , United States

RTL DFT Verification

Posted July 22, 2026

Staff, RTL Engineer

Tenstorrent

United States; 新北市, New Taipei City, Taiwan

Verilog ASIC RTL

Posted July 22, 2026

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