MTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
The FEINT Engineer is responsible for RTL quality check, power aware synthesis, netlist check and delivery with high quality and timely. Provide the support on constrain, upf and EDA tools to design team. Provide the support on floorplan, CTS and timing closure to physical design team.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, verification and implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology
- Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team
PREFERRED EXPERIENCE:
- MS degree of EE, 7~10 years working experience
- Experience with Verilog RTL design/implementation and has experience of large digital ASIC project
- Experience with front-end EDA tools and flows (Fusion compiler, PrimeTime, Conformal, VSI/VCLP, Formality/LEC, etc…)
- Experience with unix/linux and scripts (tcl, perl, etc.)
- Experience with physical design is a plus
- Has Synthesis or physical implement experience
- Experience with lower power design methodology
- Good English skills on talking, presentation and writing documents
- Good communication and strong sense of responsibility, task scheduling, and time management
ACADEMIC CREDENTIALS:
- Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.
LOCATIONS:
- Taipei
- Hsinchu
#LI-SC1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
The FEINT Engineer is responsible for RTL quality check, power aware synthesis, netlist check and delivery with high quality and timely. Provide the support on constrain, upf and EDA tools to design team. Provide the support on floorplan, CTS and timing closure to physical design team.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, verification and implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology
- Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team
PREFERRED EXPERIENCE:
- MS degree of EE, 7~10 years working experience
- Experience with Verilog RTL design/implementation and has experience of large digital ASIC project
- Experience with front-end EDA tools and flows (Fusion compiler, PrimeTime, Conformal, VSI/VCLP, Formality/LEC, etc…)
- Experience with unix/linux and scripts (tcl, perl, etc.)
- Experience with physical design is a plus
- Has Synthesis or physical implement experience
- Experience with lower power design methodology
- Good English skills on talking, presentation and writing documents
- Good communication and strong sense of responsibility, task scheduling, and time management
ACADEMIC CREDENTIALS:
- Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.
LOCATIONS:
- Taipei
- Hsinchu
#LI-SC1