Senior Design Engineer
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SENIOR SILICON DESIGN ENGINEER
THE ROLE:
AMD is looking for Sr Silicon Design Engineer passionate about microprocessor RTL development. The ideal candidate will have experience in developing RTL, IP integration, power and performance analysis for RISC-V processors and subsystems. In this role the candidate will work with an experienced RISC-V processor design and verification team define, specify, analyze and develop new and enhanced functionality in the AMD MicroBlaze V processor and other related Intellectual Property cores for the next generation adaptable silicon devices. You will join a team whose design and development activities cover a wide range of disciplines including specification, implementation, verification, benchmarking and analysis of the processor and cache coherency architectures.
LOCATION: Gothenburg, Sweden
THE PERSON:
The ideal candidate has passion for developing RISC-V based CPUs and subsystems. Should have demonstrated experience in developing RTL, synthesis, and verification, and PPA analysis with focus on RISC-V CPUs and subsystems. Able to communicate effectively and work optimally with different teams across AMD.
KEY RESPONSIBLITIES:
- RTL development, IP integration, Synthesis, and verification of AMD RISC-V CPUs and subsystems
- Perform analysis to achieve best power, performance and area of RISC-V CPUs and subsystems across multiple Adaptive SOCs
- Automate generation of RISC-V subsystems for multiple configurations
- Stay informed on latest trends on innovations on low power hardware architecture and implementation
- Technically interact with internal engineering teams, support teams and external customers
- Author product and user guides for the team Intellectual Property cores
- Teamwork across multiple geographical sites
PREFERRED EXPERIENCE:
- Proven track record of developing RTL for modern IP and SOC microarchitectures
- Experience with both FPGA and ASIC design implementations
- Strong VHDL and System Verilog experience
- Experience with subsystem and IP analysis and optimization
- Experience optimizing and performing PPA tradeoff analysis
- Strong C programming experience
- Experience performing IP integration, lint and debug
- Experience with RISC-V based CPUs and subsystems
- Deep knowledge of front-end tools
- Experience with synthesis, static timing, DFT
- Exposure to physical design and verification methods
- Experience with scripting languages such as Perl, Python, Unix shells and Makefiles
ACADEMIC CREDENTIALS:
- Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or related equivalent
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SENIOR SILICON DESIGN ENGINEER
THE ROLE:
AMD is looking for Sr Silicon Design Engineer passionate about microprocessor RTL development. The ideal candidate will have experience in developing RTL, IP integration, power and performance analysis for RISC-V processors and subsystems. In this role the candidate will work with an experienced RISC-V processor design and verification team define, specify, analyze and develop new and enhanced functionality in the AMD MicroBlaze V processor and other related Intellectual Property cores for the next generation adaptable silicon devices. You will join a team whose design and development activities cover a wide range of disciplines including specification, implementation, verification, benchmarking and analysis of the processor and cache coherency architectures.
LOCATION: Gothenburg, Sweden
THE PERSON:
The ideal candidate has passion for developing RISC-V based CPUs and subsystems. Should have demonstrated experience in developing RTL, synthesis, and verification, and PPA analysis with focus on RISC-V CPUs and subsystems. Able to communicate effectively and work optimally with different teams across AMD.
KEY RESPONSIBLITIES:
- RTL development, IP integration, Synthesis, and verification of AMD RISC-V CPUs and subsystems
- Perform analysis to achieve best power, performance and area of RISC-V CPUs and subsystems across multiple Adaptive SOCs
- Automate generation of RISC-V subsystems for multiple configurations
- Stay informed on latest trends on innovations on low power hardware architecture and implementation
- Technically interact with internal engineering teams, support teams and external customers
- Author product and user guides for the team Intellectual Property cores
- Teamwork across multiple geographical sites
PREFERRED EXPERIENCE:
- Proven track record of developing RTL for modern IP and SOC microarchitectures
- Experience with both FPGA and ASIC design implementations
- Strong VHDL and System Verilog experience
- Experience with subsystem and IP analysis and optimization
- Experience optimizing and performing PPA tradeoff analysis
- Strong C programming experience
- Experience performing IP integration, lint and debug
- Experience with RISC-V based CPUs and subsystems
- Deep knowledge of front-end tools
- Experience with synthesis, static timing, DFT
- Exposure to physical design and verification methods
- Experience with scripting languages such as Perl, Python, Unix shells and Makefiles
ACADEMIC CREDENTIALS:
- Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or related equivalent
#LI-RA1
#LI-HYBRID