Silicon Design Engineer / IC Design Engineer Intern
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
LOCATION: Singapore
CRITERIA: Current students studying in Universities which are based in Singapore
INTERNSHIP DURATION: minimum 20 weeks full time commitment with the option of extending up to a further 12 weeks.
Intern - Silicon Design Engineer / IC Design Engineer
WHAT YOU CAN EXPECT TO LEARN:
- Gain industry experience working on the latest technology process nodes.
- Join us and learn about how fulfilling a career in IC design can be!
- As we have various disciplines within IC design, we would get to know you better through the application process and assign you to the most suitable team to best fit you!
PROJECT OVERVIEW:
Jump start your IC design journey by being part of a dynamic team covering many areas including but not limited to analog design and implementation, digital design and implementation, functional verification, post-silicon validation, and many more!
You will be part of the SerDes Technology team and get the opportunity to collaborate with our teams around the globe. Being alongside engineers across different disciplines means that you would get a better understanding of the differences between different disciplines so that you are able to make an informed decision on which path to pursue when you join us after your graduation.
KEY RESPONSIBILITIES:
- First few weeks
- Get to know more about Singapore Design Team at AMD
- Strengthen foundational technical IC design knowledge
- Get comfortable working independently as well as in a team environment across multiple geographical sites.
- Next few months
- Develop soft skills such as communication and presentation by participating in technical discussions and conduct knowledge sharing sessions
- Be able to appreciate the considerations when making engineering judgement decisions
- Work on projects as part of specialization (see details in section below)
- Throughout the internship
- Participate in company/department events, social events, recreation events, etc
WHO ARE WE LOOKING FOR:
- A self-driven individual with a willingness to learn, resourceful and passionate about technology. Willingness to learn with a good attitude. Willing to work hard and play hard!
RELEVANT SKILLSETS:
- Degree/Master/PhD in Electronics/Electrical/Computer Engineering/Computer Science
- Scripting skills (eg. Perl, TCL, shell, Python) beneficial
- Fast learner and ready to solve problems
- Excellent problem-solving and communication skills
- Ability to work collaboratively in a team-oriented environment
SPECIALIZATIONS: (would be attached to one of the following)
- Analog design
- Design and development of high speed analog and mix signal circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
- Use, simulate and analyze log and report generated from EDA tools and make design trade-off to get the required results within the scheduled milestones
- Learn the architecture and design of SERDES block (Transmitter, receiver, pll etc)
- Basic scripting and programming (Unix, Pytthon, Perl)
- Familiarization with IC design tools (Cadence ADE/Spectre, Synopsys Hspice/XA, etc)
- Learn and understand IC design flow to implement circuit design
- Candidates will have the opportunity to explore cross function experience eg RTL/Layout/STA/Verification
- Analog layout implementation
- Layout implementation in high speed circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
- Perform various physical verification checks such as Layout-versus-Schematic (LVS) and Design Rule Check (DRC) to meet circuit function, performance, and process requirements
- Understand basic Process Design Rules and differences in metal schemes.
- Basic scripting and programming (Unix, Pytthon, Perl)
- Familiarization with IC design tools (Cadence Virtuoso , Calibre, etc)
- Learn and understand IC design flow to implement layout design
- Candidates will have the opportunity to explore cross function experience eg RTL/Circuit /PnR/STA/Verification
- Analog static timing analysis
- Developing timing models for advanced technology nodes mixed signal circuits and complex standard cells.
- To enable a good static timing analysis run, work with various stakeholders (design, layout and integration team) to build constraints, tune design hierarchy level, review timing report to have a timing model generated.
- To ensure quality of models generated, developing and updating quality check scripts.
- Release and maintenance of the timing model databases.
- Evaluate best in class EDA tools and flow in the industry.
- Digital design
- Roles
- Digital Design
- Low Power design explorations
- Design digital logic blocks in Verilog (RTL)
- Develop testbench and functional verification of developed digital logic blocks.
- Silicon validation
- Develop Emulation platform using Python and CocoTB (https://www.cocotb.org/ )
- Post silicon validation, testing and debug of block functionality on prototype silicon.
- Next generation RTL/AI tool
- Explore new approaches to improve RTL quality and productivity.
- Explore AI/ML to improve RTL methodology.
- Preferred skills
- Good fundamental of digital logic design is preferred.
- Experience in Verilog and/or VHDL is preferred.
- Good programming/scripting skills (Python, OOP concepts, Perl, etc) is preferred.
- Digital IP development (AI/ML & network security)
- Overview
- We are seeking a highly motivated and technically proficient Network Security Intern with a focus on Artificial Intelligence/Machine Learning (AI/ML) and Field-Programmable Gate Arrays (FPGAs). The successful candidate will work closely with our team to develop and implement cutting-edge FPGA intellectual properties that leverage AI/ML techniques to enhance the network security.
- Roles
- AI/ML Integration:
- Collaborate with the network security team to identify opportunities for integrating AI/ML algorithms into existing security protocols.
- Implement, test, and optimize machine learning models for threat detection and anomaly identification.
- FPGA Development:
- Design, develop, and optimize FPGA-based solutions to accelerate key network security functions.
- Implement hardware-accelerated algorithms to enhance the performance and efficiency of security measures.
- Network Security Enhancement:
- Investigate and address security vulnerabilities through the implementation of advanced technologies, including AI/ML and FPGA-based solutions.
- Research and Innovation:
- Stay abreast of the latest developments in AI/ML, FPGA technology, and network security.
- Conduct research to identify emerging threats and propose innovative solutions to strengthen network security.
- Preferred skills
- Strong programming skills in languages such as Python, C/C++, or Verilog.
- Familiarity with AI/ML frameworks (e.g., TensorFlow, PyTorch) and FPGA development tools.
- Understanding of network security principles, protocols, and common attack vectors.
- Solid understanding of hardware/software co-design and optimization.
- Experience with FPGA development boards and toolchains.
- Knowledge of hardware-accelerated computing and parallel processing.
- Familiarity with cybersecurity best practices and methodologies.
- Excellent problem-solving and communication skills.
- Ability to work collaboratively in a team-oriented environment.
- Digital implementation
- Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys Design Compiler, IC Compiler 2, Fusion Compiler
- Implement P&R designs using the latest technology from 3nm to 16nm node process
- Develop and implement plans to synthesize and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
- Design complex clock structure to meet tight skew requirements
- Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
- Ensure the implemented design meets all DRC required for process node below 16nm as well as DFM.
- Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
- Digital static timing analysis
- Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys PrimeTime
- Develop timing constraints to enable static timing analysis
- Simulate and analyse logs/reports generated from EDA tools (mainly ICC2 and Primetime) and make design trade-off to get the required results within the scheduled milestones.
- Functional verification
- Roles
- Functional verification of SerDes and/or Security IP design blocks
- Participate in testbench environment design and implementation in SystemVerilog/UVM-based framework and/or Python-based framework.
- Execute and manage regressions and work closely with design team to debug, identify, and resolve design bugs.
- Perform coverage analysis to ensure all design features are verified.
- Simulation framework development
- Participate in development of automation and/or hardware acceleration to improve engineering efficiency and productivity.
- Participate in exploration of incorporating AI/ML into automation framework.
- Next generation verification methodology exploration
- Participate in exploration of new approach to improve verification quality and productivity.
- Participate in exploration of incorporating AI/ML into verification methodology.
- Preferred skills
- Good fundamental of digital logic design is preferred.
- Experience in SystemVerilog and/or UVM is preferred.
- Good programming/scripting skills (Python, C/C++, Perl, Ruby, Java, etc) is preferred.
- Experience in AI/ML related project is preferred.
- Post-silicon validation
- Roles
- Post silicon validation of high speed SerDes.
- SerDes bring up, functional verification and performance optimization.
- Develop validation methodology and automation scripting to characterize the latest SerDes design.
- Work with design engineer on SerDes silicon issue debug.
- Tune and optimize SerDes configuration and validate SerDes for meet various industrial compliance standards in PVT environment.
- Preferred skills
- Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL et.) for firmware development, test methodology development and test automation
- Knowledge of common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc.
#LI-CO1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
LOCATION: Singapore
CRITERIA: Current students studying in Universities which are based in Singapore
INTERNSHIP DURATION: minimum 20 weeks full time commitment with the option of extending up to a further 12 weeks.
Intern - Silicon Design Engineer / IC Design Engineer
WHAT YOU CAN EXPECT TO LEARN:
- Gain industry experience working on the latest technology process nodes.
- Join us and learn about how fulfilling a career in IC design can be!
- As we have various disciplines within IC design, we would get to know you better through the application process and assign you to the most suitable team to best fit you!
PROJECT OVERVIEW:
Jump start your IC design journey by being part of a dynamic team covering many areas including but not limited to analog design and implementation, digital design and implementation, functional verification, post-silicon validation, and many more!
You will be part of the SerDes Technology team and get the opportunity to collaborate with our teams around the globe. Being alongside engineers across different disciplines means that you would get a better understanding of the differences between different disciplines so that you are able to make an informed decision on which path to pursue when you join us after your graduation.
KEY RESPONSIBILITIES:
- First few weeks
- Get to know more about Singapore Design Team at AMD
- Strengthen foundational technical IC design knowledge
- Get comfortable working independently as well as in a team environment across multiple geographical sites.
- Next few months
- Develop soft skills such as communication and presentation by participating in technical discussions and conduct knowledge sharing sessions
- Be able to appreciate the considerations when making engineering judgement decisions
- Work on projects as part of specialization (see details in section below)
- Throughout the internship
- Participate in company/department events, social events, recreation events, etc
WHO ARE WE LOOKING FOR:
- A self-driven individual with a willingness to learn, resourceful and passionate about technology. Willingness to learn with a good attitude. Willing to work hard and play hard!
RELEVANT SKILLSETS:
- Degree/Master/PhD in Electronics/Electrical/Computer Engineering/Computer Science
- Scripting skills (eg. Perl, TCL, shell, Python) beneficial
- Fast learner and ready to solve problems
- Excellent problem-solving and communication skills
- Ability to work collaboratively in a team-oriented environment
SPECIALIZATIONS: (would be attached to one of the following)
- Analog design
- Design and development of high speed analog and mix signal circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
- Use, simulate and analyze log and report generated from EDA tools and make design trade-off to get the required results within the scheduled milestones
- Learn the architecture and design of SERDES block (Transmitter, receiver, pll etc)
- Basic scripting and programming (Unix, Pytthon, Perl)
- Familiarization with IC design tools (Cadence ADE/Spectre, Synopsys Hspice/XA, etc)
- Learn and understand IC design flow to implement circuit design
- Candidates will have the opportunity to explore cross function experience eg RTL/Layout/STA/Verification
- Analog layout implementation
- Layout implementation in high speed circuit and its auxiliary circuit block design (112Gbps and above) in advanced technology node (3nm, 7nm)
- Perform various physical verification checks such as Layout-versus-Schematic (LVS) and Design Rule Check (DRC) to meet circuit function, performance, and process requirements
- Understand basic Process Design Rules and differences in metal schemes.
- Basic scripting and programming (Unix, Pytthon, Perl)
- Familiarization with IC design tools (Cadence Virtuoso , Calibre, etc)
- Learn and understand IC design flow to implement layout design
- Candidates will have the opportunity to explore cross function experience eg RTL/Circuit /PnR/STA/Verification
- Analog static timing analysis
- Developing timing models for advanced technology nodes mixed signal circuits and complex standard cells.
- To enable a good static timing analysis run, work with various stakeholders (design, layout and integration team) to build constraints, tune design hierarchy level, review timing report to have a timing model generated.
- To ensure quality of models generated, developing and updating quality check scripts.
- Release and maintenance of the timing model databases.
- Evaluate best in class EDA tools and flow in the industry.
- Digital design
- Roles
- Digital Design
- Low Power design explorations
- Design digital logic blocks in Verilog (RTL)
- Develop testbench and functional verification of developed digital logic blocks.
- Silicon validation
- Develop Emulation platform using Python and CocoTB (https://www.cocotb.org/ )
- Post silicon validation, testing and debug of block functionality on prototype silicon.
- Next generation RTL/AI tool
- Explore new approaches to improve RTL quality and productivity.
- Explore AI/ML to improve RTL methodology.
- Preferred skills
- Good fundamental of digital logic design is preferred.
- Experience in Verilog and/or VHDL is preferred.
- Good programming/scripting skills (Python, OOP concepts, Perl, etc) is preferred.
- Digital IP development (AI/ML & network security)
- Overview
- We are seeking a highly motivated and technically proficient Network Security Intern with a focus on Artificial Intelligence/Machine Learning (AI/ML) and Field-Programmable Gate Arrays (FPGAs). The successful candidate will work closely with our team to develop and implement cutting-edge FPGA intellectual properties that leverage AI/ML techniques to enhance the network security.
- Roles
- AI/ML Integration:
- Collaborate with the network security team to identify opportunities for integrating AI/ML algorithms into existing security protocols.
- Implement, test, and optimize machine learning models for threat detection and anomaly identification.
- FPGA Development:
- Design, develop, and optimize FPGA-based solutions to accelerate key network security functions.
- Implement hardware-accelerated algorithms to enhance the performance and efficiency of security measures.
- Network Security Enhancement:
- Investigate and address security vulnerabilities through the implementation of advanced technologies, including AI/ML and FPGA-based solutions.
- Research and Innovation:
- Stay abreast of the latest developments in AI/ML, FPGA technology, and network security.
- Conduct research to identify emerging threats and propose innovative solutions to strengthen network security.
- Preferred skills
- Strong programming skills in languages such as Python, C/C++, or Verilog.
- Familiarity with AI/ML frameworks (e.g., TensorFlow, PyTorch) and FPGA development tools.
- Understanding of network security principles, protocols, and common attack vectors.
- Solid understanding of hardware/software co-design and optimization.
- Experience with FPGA development boards and toolchains.
- Knowledge of hardware-accelerated computing and parallel processing.
- Familiarity with cybersecurity best practices and methodologies.
- Excellent problem-solving and communication skills.
- Ability to work collaboratively in a team-oriented environment.
- Digital implementation
- Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys Design Compiler, IC Compiler 2, Fusion Compiler
- Implement P&R designs using the latest technology from 3nm to 16nm node process
- Develop and implement plans to synthesize and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
- Design complex clock structure to meet tight skew requirements
- Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
- Ensure the implemented design meets all DRC required for process node below 16nm as well as DFM.
- Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
- Digital static timing analysis
- Get proficient working in UNIX/LINUX environment to use Electronic Design Automation (EDA) tools such as Synopsys PrimeTime
- Develop timing constraints to enable static timing analysis
- Simulate and analyse logs/reports generated from EDA tools (mainly ICC2 and Primetime) and make design trade-off to get the required results within the scheduled milestones.
- Functional verification
- Roles
- Functional verification of SerDes and/or Security IP design blocks
- Participate in testbench environment design and implementation in SystemVerilog/UVM-based framework and/or Python-based framework.
- Execute and manage regressions and work closely with design team to debug, identify, and resolve design bugs.
- Perform coverage analysis to ensure all design features are verified.
- Simulation framework development
- Participate in development of automation and/or hardware acceleration to improve engineering efficiency and productivity.
- Participate in exploration of incorporating AI/ML into automation framework.
- Next generation verification methodology exploration
- Participate in exploration of new approach to improve verification quality and productivity.
- Participate in exploration of incorporating AI/ML into verification methodology.
- Preferred skills
- Good fundamental of digital logic design is preferred.
- Experience in SystemVerilog and/or UVM is preferred.
- Good programming/scripting skills (Python, C/C++, Perl, Ruby, Java, etc) is preferred.
- Experience in AI/ML related project is preferred.
- Post-silicon validation
- Roles
- Post silicon validation of high speed SerDes.
- SerDes bring up, functional verification and performance optimization.
- Develop validation methodology and automation scripting to characterize the latest SerDes design.
- Work with design engineer on SerDes silicon issue debug.
- Tune and optimize SerDes configuration and validate SerDes for meet various industrial compliance standards in PVT environment.
- Preferred skills
- Strong programming/scripting skills (eg. Python, C/C++, Perl, TCL et.) for firmware development, test methodology development and test automation
- Knowledge of common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA etc.
#LI-CO1