SMTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
NBIO IOHUB Subsystem Design Engineer
THE ROLE:
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles. NBIO global operates seamless from China, North America, and Europe.
IOHUB sits in the center of all data paths, it includes 1 Sub-system and 2 SUB-IP name as IOHub Core and IOMMU. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. The IOMMU (I/O Memory Management Unit) is a system function that translates addresses used in DMA transactions, protects memory from illegal access by I/O devices, and remaps peripheral interrupts. It plays a critical role on IO virtualization technology which is widely used in today’s mega-data center.
We are searching for a designer to join the fast-growing IOHUB team, and be responsible for defining, specifying, and implementing current and future IOHUB Subsystem. The candidate will work closely with global IOHUB team and SoC team.
THE PERSON:
Candidate will work as a MTS design engineer, co-operate with local engineer and co-work with global IOHUB team on IOHUB related features development, maintenance, and optimization. Candidate needs to have chip design background and good English read/write capability.
KEY RESPONSIBILITIES:
- Bridge sub-IPs and SOCs to ensure IOHUB Subsystem is deployed successfully
- Collaborate with architects, IP engineers, and verification engineers to understand the new features to be developed
- Integrate IP drop to refresh Sub-system RTL
- Build design documentation, accounting for interactions with other features, connectivity, repeater stage insertion, etc.
- Estimate the time required to implement the features/integration and any required changes to the deliver Sub-system RTL
- Support DV to debug test failures to determine the root cause, and in charge of resolve design defects
- Review functional and code coverage metrics – work with DV to modify or add tests or constrain random tests to meet the coverage requirements
- Work on IOHUB Subsystem automation solution to reduce IOHUB re-configuration effort
PREFERRED EXPERIENCE:
- Proficient in IP/SS/SOC level ASIC RTL design
- Proficient in debugging firmware and RTL code using simulation tools
- Experienced with Verilog, System Verilog, SV assertion and Makefile
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good understanding and hands-on experience in the feature implementation and SystemVerilog language
- Scripting language experience: Python, Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to PCIe system or X86 computer architecture.
- Strong collaboration skill set
ACADEMIC CREDENTIALS:
- MSEE within 5-8 years, or BSEE within 6-9 years’ experience in digital ASIC/SOC design
LOCATION:
Shanghai
#LI-VC1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
NBIO IOHUB Subsystem Design Engineer
THE ROLE:
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles. NBIO global operates seamless from China, North America, and Europe.
IOHUB sits in the center of all data paths, it includes 1 Sub-system and 2 SUB-IP name as IOHub Core and IOMMU. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. The IOMMU (I/O Memory Management Unit) is a system function that translates addresses used in DMA transactions, protects memory from illegal access by I/O devices, and remaps peripheral interrupts. It plays a critical role on IO virtualization technology which is widely used in today’s mega-data center.
We are searching for a designer to join the fast-growing IOHUB team, and be responsible for defining, specifying, and implementing current and future IOHUB Subsystem. The candidate will work closely with global IOHUB team and SoC team.
THE PERSON:
Candidate will work as a MTS design engineer, co-operate with local engineer and co-work with global IOHUB team on IOHUB related features development, maintenance, and optimization. Candidate needs to have chip design background and good English read/write capability.
KEY RESPONSIBILITIES:
- Bridge sub-IPs and SOCs to ensure IOHUB Subsystem is deployed successfully
- Collaborate with architects, IP engineers, and verification engineers to understand the new features to be developed
- Integrate IP drop to refresh Sub-system RTL
- Build design documentation, accounting for interactions with other features, connectivity, repeater stage insertion, etc.
- Estimate the time required to implement the features/integration and any required changes to the deliver Sub-system RTL
- Support DV to debug test failures to determine the root cause, and in charge of resolve design defects
- Review functional and code coverage metrics – work with DV to modify or add tests or constrain random tests to meet the coverage requirements
- Work on IOHUB Subsystem automation solution to reduce IOHUB re-configuration effort
PREFERRED EXPERIENCE:
- Proficient in IP/SS/SOC level ASIC RTL design
- Proficient in debugging firmware and RTL code using simulation tools
- Experienced with Verilog, System Verilog, SV assertion and Makefile
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good understanding and hands-on experience in the feature implementation and SystemVerilog language
- Scripting language experience: Python, Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to PCIe system or X86 computer architecture.
- Strong collaboration skill set
ACADEMIC CREDENTIALS:
- MSEE within 5-8 years, or BSEE within 6-9 years’ experience in digital ASIC/SOC design
LOCATION:
Shanghai
#LI-VC1