Silicon Validation/Emulation Design Engineer

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs. If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us! In this role, you'll be responsible for the following: - Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations. - System-level debug and root cause analysis of complex hardware issues on the emulation platform. - IP-level debug and validation, working closely with IP owners to isolate and resolve design issues. - Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization. - Performance profiling and optimization of emulation models to maximize execution speed. - Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones. BS and a minimum of 10 years relevant industry experience